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/linux-5.10/drivers/vfio/platform/
Dvfio_platform_irq.c49 if (!(vdev->irqs[index].flags & VFIO_IRQ_INFO_MASKABLE)) in vfio_platform_set_irq_mask()
56 return vfio_virqfd_enable((void *) &vdev->irqs[index], in vfio_platform_set_irq_mask()
59 &vdev->irqs[index].mask, fd); in vfio_platform_set_irq_mask()
61 vfio_virqfd_disable(&vdev->irqs[index].mask); in vfio_platform_set_irq_mask()
66 vfio_platform_mask(&vdev->irqs[index]); in vfio_platform_set_irq_mask()
72 vfio_platform_mask(&vdev->irqs[index]); in vfio_platform_set_irq_mask()
109 if (!(vdev->irqs[index].flags & VFIO_IRQ_INFO_MASKABLE)) in vfio_platform_set_irq_unmask()
116 return vfio_virqfd_enable((void *) &vdev->irqs[index], in vfio_platform_set_irq_unmask()
119 &vdev->irqs[index].unmask, in vfio_platform_set_irq_unmask()
122 vfio_virqfd_disable(&vdev->irqs[index].unmask); in vfio_platform_set_irq_unmask()
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/linux-5.10/Documentation/devicetree/bindings/arm/omap/
Dcrossbar.txt13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
24 SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
25 crossbar. These irqs have a crossbar register, but still cannot be used.
27 - ti,irqs-safe-map: integer which maps to a safe configuration to use
34 ti,max-irqs = <160>;
37 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
38 ti,irqs-skip = <10 133 139 140>;
/linux-5.10/arch/powerpc/platforms/powernv/
Dpci-cxl.c62 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, in pnv_cxl_release_hwirq_ranges() argument
70 if (!irqs->range[i]) in pnv_cxl_release_hwirq_ranges()
73 i, irqs->offset[i], in pnv_cxl_release_hwirq_ranges()
74 irqs->range[i]); in pnv_cxl_release_hwirq_ranges()
75 hwirq = irqs->offset[i] - phb->msi_base; in pnv_cxl_release_hwirq_ranges()
77 irqs->range[i]); in pnv_cxl_release_hwirq_ranges()
82 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, in pnv_cxl_alloc_hwirq_ranges() argument
89 memset(irqs, 0, sizeof(struct cxl_irq_ranges)); in pnv_cxl_alloc_hwirq_ranges()
103 irqs->offset[i] = phb->msi_base + hwirq; in pnv_cxl_alloc_hwirq_ranges()
104 irqs->range[i] = try; in pnv_cxl_alloc_hwirq_ranges()
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/linux-5.10/drivers/bus/fsl-mc/
Dfsl-mc-allocator.c339 * ID. A block of IRQs is pre-allocated and maintained in a pool
345 * It allocates a block of IRQs from the GIC-ITS.
412 * It frees the IRQs that were allocated to the pool, back to the GIC-ITS.
438 * Allocate the IRQs required by a given fsl-mc device.
446 struct fsl_mc_device_irq **irqs = NULL; in fsl_mc_allocate_irqs() local
450 if (mc_dev->irqs) in fsl_mc_allocate_irqs()
468 "Not able to allocate %u irqs for device\n", irq_count); in fsl_mc_allocate_irqs()
472 irqs = devm_kcalloc(&mc_dev->dev, irq_count, sizeof(irqs[0]), in fsl_mc_allocate_irqs()
474 if (!irqs) in fsl_mc_allocate_irqs()
485 irqs[i] = to_fsl_mc_irq(resource); in fsl_mc_allocate_irqs()
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/linux-5.10/drivers/gpio/
Dgpio-davinci.c64 int irqs[MAX_INT_PER_BANK]; member
239 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
240 if (chips->irqs[i] < 0) in davinci_gpio_probe()
241 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n"); in davinci_gpio_probe()
281 * We expect irqs will normally be set up as input pins, but they can also be
356 /* ack any irqs */ in gpio_irq_handler()
395 * NOTE: we assume for now that only irqs in the first gpio_chip in gpio_to_irq_unbanked()
396 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
399 return d->irqs[offset]; in gpio_to_irq_unbanked()
413 if (data->irq == d->irqs[i]) in gpio_irq_type_unbanked()
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Dgpio-reg.c20 const int *irqs; member
102 int irq = r->irqs[offset]; in gpio_reg_to_irq()
120 * @irqs: array of %num ints describing the interrupt mapping for each
133 const char *const *names, struct irq_domain *irqdom, const int *irqs) in gpio_reg_init() argument
155 if (irqs) in gpio_reg_init()
163 r->irqs = irqs; in gpio_reg_init()
/linux-5.10/kernel/irq/
Dtimings.c382 static u64 __irq_timings_next_event(struct irqt_stat *irqs, int irq, u64 now) in __irq_timings_next_event() argument
386 if ((now - irqs->last_ts) >= NSEC_PER_SEC) { in __irq_timings_next_event()
387 irqs->count = irqs->last_ts = 0; in __irq_timings_next_event()
396 period_max = irqs->count > (3 * PREDICTION_PERIOD_MAX) ? in __irq_timings_next_event()
397 PREDICTION_PERIOD_MAX : irqs->count / 3; in __irq_timings_next_event()
409 count = irqs->count < IRQ_TIMINGS_SIZE ? in __irq_timings_next_event()
410 irqs->count : IRQ_TIMINGS_SIZE; in __irq_timings_next_event()
412 start = irqs->count < IRQ_TIMINGS_SIZE ? in __irq_timings_next_event()
413 0 : (irqs->count & IRQ_TIMINGS_MASK); in __irq_timings_next_event()
424 irqs->timings[i] = irqs->circ_timings[index]; in __irq_timings_next_event()
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/linux-5.10/drivers/irqchip/
Dirq-nvic.c33 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
34 * 16 irqs.
76 unsigned int irqs, i, ret, numbanks; in nvic_of_init() local
88 irqs = numbanks * 32; in nvic_of_init()
89 if (irqs > NVIC_MAX_IRQ) in nvic_of_init()
90 irqs = NVIC_MAX_IRQ; in nvic_of_init()
93 irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL); in nvic_of_init()
128 for (i = 0; i < irqs; i += 4) in nvic_of_init()
Dirq-bcm6345-l1.c19 * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
20 * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
23 * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
24 * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
31 * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
32 * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
33 * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
34 * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
39 * 0x1000_0050: CPU1_W0_STATUS IRQs 96-127
40 * 0x1000_0054: CPU1_W1_STATUS IRQs 64-95
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Dirq-crossbar.c144 * @nr_irqs: number of irqs to free
219 of_property_read_u32(node, "ti,max-irqs", &max); in crossbar_of_init()
221 pr_err("missing 'ti,max-irqs' property\n"); in crossbar_of_init()
234 /* Get and mark reserved irqs */ in crossbar_of_init()
235 irqsr = of_get_property(node, "ti,irqs-reserved", &size); in crossbar_of_init()
241 "ti,irqs-reserved", in crossbar_of_init()
252 /* Skip irqs hardwired to bypass the crossbar */ in crossbar_of_init()
253 irqsr = of_get_property(node, "ti,irqs-skip", &size); in crossbar_of_init()
259 "ti,irqs-skip", in crossbar_of_init()
296 * reserved irqs. so find and store the offsets once. in crossbar_of_init()
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Dirq-ingenic-tcu.c94 int ret, irqs; in ingenic_tcu_irq_init() local
106 irqs = of_property_count_elems_of_size(np, "interrupts", sizeof(u32)); in ingenic_tcu_irq_init()
107 if (irqs < 0 || irqs > ARRAY_SIZE(tcu->parent_irqs)) { in ingenic_tcu_irq_init()
113 tcu->nb_parent_irqs = irqs; in ingenic_tcu_irq_init()
144 /* Mask all IRQs by default */ in ingenic_tcu_irq_init()
157 for (i = 0; i < irqs; i++) { in ingenic_tcu_irq_init()
/linux-5.10/drivers/pci/controller/
Dvmd.c81 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
84 * @count: number of child IRQs assigned to this vector; used to track
100 struct vmd_irq_list *irqs; member
115 struct vmd_irq_list *irqs) in index_from_irqs() argument
117 return irqs - vmd->irqs; in index_from_irqs()
121 * Drivers managing a device in a VMD domain allocate their own IRQs as before,
206 return &vmd->irqs[0]; in vmd_next_irq()
216 return &vmd->irqs[0]; in vmd_next_irq()
221 if (vmd->irqs[i].count < vmd->irqs[best].count) in vmd_next_irq()
223 vmd->irqs[best].count++; in vmd_next_irq()
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/linux-5.10/drivers/pci/pcie/
Dportdrv_core.c96 * @irqs: Array of interrupt vectors to populate
101 static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) in pcie_port_enable_irq_vec() argument
143 irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pcie_irq; in pcie_port_enable_irq_vec()
144 irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pcie_irq; in pcie_port_enable_irq_vec()
145 irqs[PCIE_PORT_SERVICE_BWNOTIF_SHIFT] = pcie_irq; in pcie_port_enable_irq_vec()
149 irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, aer); in pcie_port_enable_irq_vec()
152 irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, dpc); in pcie_port_enable_irq_vec()
158 * pcie_init_service_irqs - initialize irqs for PCI Express port services
160 * @irqs: Array of irqs to populate
165 static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask) in pcie_init_service_irqs() argument
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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dst,sti-irq-syscfg.txt1 STMicroelectronics STi System Configuration Controlled IRQs
5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
15 - st,irq-device : Array of IRQs to enable - should be 2 in length
19 - st,invert-ext : External IRQs can be inverted at will. This property inverts
20 these IRQs using bitwise logic. A number of defines have been
/linux-5.10/drivers/staging/media/atomisp/pci/
Dgp_timer_defs.h28 …IVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(… argument
29 …GP_TIMER_IRQ_ENABLE_REG_IDX(irq, timers, irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs,… argument
/linux-5.10/drivers/power/supply/
Daxp20x_ac_power.c49 unsigned int irqs[]; member
294 * As nested threaded IRQs are not automatically disabled during in axp20x_ac_power_suspend()
295 * suspend, we must explicitly disable the remainder of the IRQs. in axp20x_ac_power_suspend()
298 enable_irq_wake(power->irqs[i++]); in axp20x_ac_power_suspend()
300 disable_irq(power->irqs[i++]); in axp20x_ac_power_suspend()
311 disable_irq_wake(power->irqs[i++]); in axp20x_ac_power_resume()
313 enable_irq(power->irqs[i++]); in axp20x_ac_power_resume()
341 struct_size(power, irqs, axp_data->num_irq_names), in axp20x_ac_power_probe()
377 /* Request irqs after registering, as irqs may trigger immediately */ in axp20x_ac_power_probe()
385 power->irqs[i] = regmap_irq_get_virq(axp20x->regmap_irqc, irq); in axp20x_ac_power_probe()
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/linux-5.10/drivers/pcmcia/
Dsa1111_generic.c142 int i, ret = 0, irqs[NUM_IRQS]; in sa1111_pcmcia_add() local
149 irqs[i] = sa1111_get_irq(dev, i); in sa1111_pcmcia_add()
150 if (irqs[i] <= 0) in sa1111_pcmcia_add()
151 return irqs[i] ? : -ENXIO; in sa1111_pcmcia_add()
167 s->soc.socket.pci_irq = irqs[IDX_IRQ_S1_READY_NINT]; in sa1111_pcmcia_add()
168 s->soc.stat[SOC_STAT_CD].irq = irqs[IDX_IRQ_S1_CD_VALID]; in sa1111_pcmcia_add()
170 s->soc.stat[SOC_STAT_BVD1].irq = irqs[IDX_IRQ_S1_BVD1_STSCHG]; in sa1111_pcmcia_add()
173 s->soc.socket.pci_irq = irqs[IDX_IRQ_S0_READY_NINT]; in sa1111_pcmcia_add()
174 s->soc.stat[SOC_STAT_CD].irq = irqs[IDX_IRQ_S0_CD_VALID]; in sa1111_pcmcia_add()
176 s->soc.stat[SOC_STAT_BVD1].irq = irqs[IDX_IRQ_S0_BVD1_STSCHG]; in sa1111_pcmcia_add()
/linux-5.10/Documentation/power/
Dsuspend-and-interrupts.rst9 Suspending and Resuming Device IRQs
12 Device interrupt request lines (IRQs) are generally disabled during system
21 interrupt handlers for shared IRQs that device drivers implementing them were
29 Device IRQs are re-enabled during system resume, right before the "early" phase
91 not executed for system wakeup IRQs. They are only executed for IRQF_NO_SUSPEND
92 IRQs at that time, but those IRQs should not be configured for system wakeup
126 Second, both enable_irq_wake() and IRQF_NO_SUSPEND apply to entire IRQs and not
133 must be able to discern spurious IRQs from genuine wakeup events (signalling
/linux-5.10/include/linux/mfd/
Drohm-bd70528.h161 /* IRQs */
163 /* Shutdown register IRQs */
171 /* Power failure register IRQs */
180 /* VR FAULT register IRQs */
192 /* Charger 1 register IRQs */
201 /* Charger 2 register IRQs */
210 /* RTC register IRQs */
213 /* GPIO register IRQs */
218 /* Invalid operation register IRQs */
/linux-5.10/arch/arc/kernel/
Dintc-arcv2.c17 unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; member
19 unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
61 * Linux by default uses lower prio 1 for most irqs, reserving 0 for in arc_init_IRQ()
79 for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { in arc_init_IRQ()
84 * Only mask cpu private IRQs here. in arc_init_IRQ()
136 * core intc IRQs [16, 23]: in arcv2_irq_map()
168 nr_cpu_irqs = irq_bcr.irqs + NR_EXCEPTIONS; in init_onchip_IRQ()
Dintc-compact.c22 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
32 * Write to register, even if no LV2 IRQs configured to reset it in arc_init_IRQ()
59 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
60 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
145 * soft ISR are low prioity jobs which can be very slow, thus all IRQs
148 * still we must re-enable both L1 and L2 IRQs
/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_gt_irq.c224 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ in gen11_gt_irq_reset()
239 const u32 irqs = in gen11_gt_irq_postinstall() local
245 const u32 dmask = irqs << 16 | irqs; in gen11_gt_irq_postinstall()
246 const u32 smask = irqs << 16; in gen11_gt_irq_postinstall()
248 BUILD_BUG_ON(irqs & 0xffff0000); in gen11_gt_irq_postinstall()
254 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ in gen11_gt_irq_postinstall()
378 const u32 irqs = in gen8_gt_irq_postinstall() local
384 irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT, in gen8_gt_irq_postinstall()
385 irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT, in gen8_gt_irq_postinstall()
387 irqs << GEN8_VECS_IRQ_SHIFT, in gen8_gt_irq_postinstall()
/linux-5.10/arch/arm/mach-sa1100/include/mach/
Dirqs.h3 * arch/arm/mach-sa1100/include/mach/irqs.h
9 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
78 * within sensible limits. IRQs 61 to 76 are available.
87 * allocate their IRQs above NR_IRQS.
89 * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
/linux-5.10/arch/powerpc/platforms/ps3/
Dspu.c246 0, &spu->irqs[0]); in setup_interrupts()
252 1, &spu->irqs[1]); in setup_interrupts()
258 2, &spu->irqs[2]); in setup_interrupts()
266 ps3_spe_irq_destroy(spu->irqs[1]); in setup_interrupts()
268 ps3_spe_irq_destroy(spu->irqs[0]); in setup_interrupts()
270 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0; in setup_interrupts()
316 ps3_spe_irq_destroy(spu->irqs[2]); in ps3_destroy_spu()
317 ps3_spe_irq_destroy(spu->irqs[1]); in ps3_destroy_spu()
318 ps3_spe_irq_destroy(spu->irqs[0]); in ps3_destroy_spu()
320 spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0; in ps3_destroy_spu()
/linux-5.10/drivers/misc/cxl/
Dirq.c191 irq_off = hwirq - ctx->irqs.offset[r]; in cxl_irq_afu()
192 range = ctx->irqs.range[r]; in cxl_irq_afu()
310 if ((rc = cxl_ops->alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter, in afu_allocate_irqs()
316 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; in afu_allocate_irqs()
317 ctx->irqs.range[0] = 1; in afu_allocate_irqs()
328 * actual hardware IRQs. in afu_allocate_irqs()
331 for (i = 0; i < ctx->irqs.range[r]; i++) { in afu_allocate_irqs()
351 cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter); in afu_allocate_irqs()
366 hwirq = ctx->irqs.offset[r]; in afu_register_hwirqs()
367 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) { in afu_register_hwirqs()
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