Searched full:hstx (Results 1 – 25 of 25) sorted by relevance
/linux-6.8/Documentation/devicetree/bindings/phy/ |
D | qcom,qusb2-phy.yaml | 114 qcom,hstx-trim-value: 116 It is a 4 bit value that specifies tuning for HSTX 137 It is a 1 bit value that specifies how long the HSTX 178 qcom,hstx-trim-value: false
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D | realtek,usb2phy.yaml | 96 realtek,inverse-hstx-sync-clock: 148 realtek,inverse-hstx-sync-clock: false 172 realtek,inverse-hstx-sync-clock;
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/linux-6.8/Documentation/devicetree/bindings/nvmem/ |
D | qcom,qfprom.yaml | 100 hstx-trim-primary@25b { 118 hstx-trim-primary@1eb {
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/linux-6.8/include/dt-bindings/phy/ |
D | phy-qcom-qusb2.h | 9 /* PHY HSTX TRIM bit values (24mA to 15mA) */
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/linux-6.8/Documentation/devicetree/bindings/display/msm/ |
D | dsi-phy-10nm.yaml | 64 for the HSTX drive. Use supported levels (mV) to offset the drive level
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/linux-6.8/arch/arm64/boot/dts/qcom/ |
D | sdm850-samsung-w737.dts | 607 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 635 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
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D | sdm850-lenovo-yoga-c630.dts | 752 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 780 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
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D | sdm845-mtp.dts | 748 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 782 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
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D | sdm845-samsung-starqltechn.dts | 409 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
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D | sdm845-db845c.dts | 1067 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 1095 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
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D | sdm845-xiaomi-beryllium-common.dtsi | 566 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
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D | sdm845-cheza.dtsi | 967 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 989 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
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D | sdm845-lg-common.dtsi | 539 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
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D | sdm845-xiaomi-polaris.dts | 664 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
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D | sdm845-oneplus-common.dtsi | 791 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
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D | qcm2290.dtsi | 729 qusb2_hstx_trim: hstx-trim@25b {
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D | sdm670.dtsi | 608 qusb2_hstx_trim: hstx-trim@1eb {
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D | sdm630.dtsi | 587 qusb2_hstx_trim: hstx-trim@240 {
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D | sdm845.dtsi | 1220 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1225 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
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D | msm8998.dtsi | 874 qusb2_hstx_trim: hstx-trim@23a {
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D | sm6115.dtsi | 928 qusb2_hstx_trim: hstx-trim@25b {
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D | sc7180.dtsi | 815 qusb2p_hstx_trim: hstx-trim-primary@25b {
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/linux-6.8/drivers/phy/qualcomm/ |
D | phy-qcom-qusb2.c | 1021 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); in qusb2_phy_probe() 1042 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
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/linux-6.8/drivers/gpu/drm/bridge/cadence/ |
D | cdns-dsi-core.c | 820 * HSTX and LPRX timeouts are both expressed in TX byte clk cycles and in cdns_dsi_bridge_enable()
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/linux-6.8/drivers/gpu/drm/vc4/ |
D | vc4_dsi.c | 1513 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout"); in vc4_dsi_irq_handler()
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