Searched full:harts (Results 1 – 21 of 21) sorted by relevance
| /linux-6.8/arch/riscv/kernel/ |
| D | sbi.c | 125 * sbi_shutdown() - Remove all the harts from executing supervisor code.
369 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
370 * @cpu_mask: A cpu mask containing all the target harts.
383 * remote harts for a virtual address range belonging to a specific ASID or not.
385 * @cpu_mask: A cpu mask containing all the target harts.
409 * harts for the specified guest physical address range.
410 * @cpu_mask: A cpu mask containing all the target harts.
427 * remote harts for a guest physical address range belonging to a specific VMID.
429 * @cpu_mask: A cpu mask containing all the target harts.
448 * harts for the current guest virtual address range.
[all …]
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| D | machine_kexec.c | 102 * harts and possibly devices etc) for a kexec reboot.
176 * executed. We assume at this point that all other harts are
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| D | cpu.c | 282 * denominator of extensions supported across all harts. A true list of in c_show()
306 * additional extensions not present across all harts. in c_show()
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| D | sys_hwprobe.c | 184 * extensions are supported on all harts, and only supports the in hwprobe_one_pair()
392 * all harts, then assume all CPUs are the same, and allow the vDSO to in init_hwprobe_vdso_data()
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| D | head.S | 186 /* We lack SMP support or have too many harts, so park this hart */
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| D | cpufeature.c | 632 * All "okay" harts should have same isa. Set HWCAP based on in riscv_fill_hwcap_from_ext_list()
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| /linux-6.8/arch/riscv/mm/ |
| D | cacheflush.c | 34 * informs the remote harts they need to flush their local instruction caches.
37 * IPIs for harts that are not currently executing a MM context and instead
57 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
119 pr_warn("%s mismatched between harts %lu and %lu\n", in cbo_get_block_size()
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| D | context.c | 212 * The mm_cpumask indicates which harts' TLBs contain the virtual in set_mm()
289 * shoot downs, so instead we send an IPI that informs the remote harts they
292 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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| /linux-6.8/drivers/acpi/riscv/ |
| D | rhct.c | 107 pr_warn("CBOM size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
114 pr_warn("CBOZ size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
121 pr_warn("CBOP size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
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| /linux-6.8/Documentation/arch/riscv/ |
| D | uabi.rst | 49 RISC-V ISA extensions recognized by the kernel and implemented on all harts. The
52 be present on all harts in the system.
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| D | boot.rst | 68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
69 wins a lottery and executes the early boot code while the other harts are
73 initialization phase and then will start all other harts using the SBI HSM
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| /linux-6.8/tools/testing/selftests/riscv/hwprobe/ |
| D | cbo.c | 152 ksft_exit_fail_msg("Zicboz is only present on a subset of harts.\n" in check_no_zicboz_cpus()
153 "Use taskset to select a set of harts where Zicboz\n" in check_no_zicboz_cpus()
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| /linux-6.8/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| D | sifive,plic-1.0.0.yaml | 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /linux-6.8/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /linux-6.8/arch/csky/abiv2/ |
| D | cacheflush.c | 81 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
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| /linux-6.8/drivers/clocksource/ |
| D | timer-riscv.c | 80 * It is guaranteed that all the timers across all the harts are synchronized
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| /linux-6.8/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 24 having four harts.
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| /linux-6.8/drivers/perf/ |
| D | riscv_pmu_sbi.c | 58 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
59 * per_cpu in case of harts with different pmu counters
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| /linux-6.8/arch/riscv/kvm/ |
| D | aia.c | 585 * run on other HARTs in kvm_riscv_aia_disable()
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| /linux-6.8/Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
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