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/qemu/hw/i386/
H A Dpc_sysfw.c37 #include "hw/block/flash.h"
67 /* copy ISA rom image from top of flash memory */ in pc_isa_bios_init()
104 pcms->flash[0] = pc_pflash_create(pcms, "system.flash0", in pc_system_flash_create()
106 pcms->flash[1] = pc_pflash_create(pcms, "system.flash1", in pc_system_flash_create()
118 for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { in pc_system_flash_cleanup_unused()
119 if (!qdev_is_realized(DEVICE(pcms->flash[i]))) { in pc_system_flash_cleanup_unused()
123 object_unparent(OBJECT(pcms->flash[i])); in pc_system_flash_cleanup_unused()
124 pcms->flash[i] = NULL; in pc_system_flash_cleanup_unused()
130 * Map the pcms->flash[] from 4GiB downward, and realize.
131 * Map them in descending order, i.e. pcms->flash[0] at the top,
[all …]
/qemu/include/hw/ssi/
H A Dnpcm7xx_fiu.h2 * Nuvoton NPCM7xx Flash Interface Unit (FIU)
31 * struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
32 * @direct_access: Memory region for direct flash access.
33 * @fiu: Pointer to flash controller shared state.
41 * NPCM7xxFIUState - Device state for one Flash Interface Unit.
44 * @cs_count: Number of flash chips that may be connected to this module.
46 * @cs_lines: GPIO lines that may be wired to flash chips.
47 * @flash: Array of @cs_count per-flash-chip state objects.
53 * read and write the flash connected to that chip select as if it were memory.
64 NPCM7xxFIUFlash *flash; member
/qemu/hw/ssi/
H A Dnpcm7xx_fiu.c2 * Nuvoton NPCM7xx Flash Interface Unit (FIU)
31 /* Up to 128 MiB of flash may be accessed directly as memory. */
103 * Returns the index of flash in the fiu->flash array. This corresponds to the
104 * chip select ID of the flash.
107 NPCM7xxFIUFlash *flash) in npcm7xx_fiu_cs_index() argument
109 int index = flash - fiu->flash; in npcm7xx_fiu_cs_index()
145 /* Direct flash memory read handler. */
158 "%s: direct flash read with CS%d already active", in npcm7xx_fiu_flash_read()
183 /* Flash chip model expects one transfer per dummy bit, not byte */ in npcm7xx_fiu_flash_read()
202 /* Direct flash memory write handler. */
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/qemu/hw/block/
H A Dm25p80.c2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
28 #include "hw/block/flash.h"
479 struct Flash { struct
534 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80) in OBJECT_DECLARE_TYPE() argument
536 static inline Manufacturer get_man(Flash *s) in OBJECT_DECLARE_TYPE()
569 static void flash_sync_page(Flash *s, int page) in flash_sync_page()
585 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) in flash_sync_area()
600 static void flash_erase(Flash *s, int offset, FlashCMD cmd) in flash_erase()
652 static inline void flash_sync_dirty(Flash *s, int64_t newpage) in flash_sync_dirty()
661 void flash_write8(Flash *s, uint32_t addr, uint8_t data) in flash_write8()
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H A Dpflash_cfi01.c2 * CFI parallel flash with Intel command set emulation
24 * - flash read
25 * - flash write
26 * - flash ID read
31 * It does not support flash interleaving
41 #include "hw/block/flash.h"
72 uint8_t wcycle; /* if 0, the flash is read normally */
134 * Perform a CFI query based on the bank width of the flash.
136 * this flash.
197 /* Perform a device id query based on the bank width of the flash. */
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H A Dpflash_cfi02.c2 * CFI parallel flash with AMD command set emulation
23 * - flash read
24 * - flash write
25 * - flash ID read
31 * It does not support flash interleaving.
37 #include "hw/block/flash.h"
81 int wcycle; /* if 0, the flash is read normally */
96 * The device replicates the flash memory across its memory space. Emulate
98 * (.mem_mappings) pointing to the flash memory (.orig_mem).
247 /* Reset flash */ in pflash_timer()
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/qemu/hw/xtensa/
H A Dxtfpga.c42 #include "hw/block/flash.h"
62 const XtfpgaFlashDesc *flash; member
180 board->flash->size / board->flash->sector_size); in xtfpga_flash_init()
181 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); in xtfpga_flash_init()
184 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); in xtfpga_flash_init()
187 memory_region_add_subregion(address_space, board->flash->base, in xtfpga_flash_init()
232 PFlashCFI01 *flash = NULL; in xtfpga_init() local
314 flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN); in xtfpga_init()
451 if (flash) { in xtfpga_init()
452 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); in xtfpga_init()
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/qemu/hw/nvram/
H A Dnrf51_nvm.c4 * It provides an interface to erase regions in flash memory.
234 memory_region_flush_rom_device(&s->flash, value, in io_write()
239 "%s: Flash erase at 0x%" HWADDR_PRIx" while flash not erasable.\n", in io_write()
247 memory_region_flush_rom_device(&s->flash, 0, s->flash_size); in io_write()
250 qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash not erasable.\n", in io_write()
295 /* NOR Flash only allows bits to be flipped from 1's to 0's on write */ in flash_write()
300 memory_region_flush_rom_device(&s->flash, offset, size); in flash_write()
303 "%s: Flash write 0x%" HWADDR_PRIx" while flash not writable.\n", in flash_write()
340 if (!memory_region_init_rom_device(&s->flash, OBJECT(dev), &flash_ops, s, in nrf51_nvm_realize()
341 "nrf51_soc.flash", s->flash_size, errp)) { in nrf51_nvm_realize()
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/qemu/docs/system/arm/
H A Daspeed.rst52 * Static Memory Controller (SMC or FMC) - Only SPI Flash support
115 Booting from a flash image
118 The machine options specific to Aspeed to boot from a flash image are :
120 * ``execute-in-place`` which emulates the boot from the CE0 flash
124 * ``fmc-model`` to change the default FMC Flash model. FW needs
127 * ``spi-model`` to change the default SPI Flash model.
129 To boot the machine from the flash image, use an MTD drive :
136 To use other flash models, for instance a different FMC chip and a
143 When more flexibility is needed to define the flash devices, to use
144 different flash models or define all flash devices (up to 8), the
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H A Dmps2.rst8 FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
45 - AN524 remapping of low memory to either BRAM or to QSPI flash is
51 - QEMU does not model the QSPI flash in MPS3 boards as real QSPI
52 flash, but only as simple ROM, so attempting to rewrite the flash
57 - AN536 does not support enabling or disabling the flash and ATCM
H A Dsx1.rst10 -pflash) V1 1 Flash of 16MB and 1 Flash of 8MB V2 1 Flash of 32MB
H A Dstellaris.rst9 - 64k Flash and 8k SRAM.
21 - 256k Flash and 64k SRAM.
/qemu/hw/arm/
H A Domap_sx1.c35 #include "hw/block/flash.h"
47 * - Boot flash 16 MB at 0x00000000
48 * - Application flash 8 MB at 0x04000000
60 * - Boot flash 32 MB at 0x00000000
104 MemoryRegion *flash = g_new(MemoryRegion, 1); in sx1_init() local
129 /* External Flash (EMIFS) */ in sx1_init()
130 memory_region_init_rom(flash, NULL, "omap_sx1.flash0-0", flash_size, in sx1_init()
132 memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash); in sx1_init()
184 error_report("Kernel or Flash image must be specified"); in sx1_init()
H A Dstm32f100_soc.c100 * Init flash region in stm32f100_soc_realize()
101 * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 in stm32f100_soc_realize()
103 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash", in stm32f100_soc_realize()
106 "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f100_soc_realize()
107 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); in stm32f100_soc_realize()
180 create_unimplemented_device("Flash Int", 0x40022000, 0x400); in stm32f100_soc_realize()
H A Dimx25_pdk.c41 * 0xa0000000-0xa7ffffff Flash IGNORED
42 * 0xa8000000-0xafffffff Flash IGNORED
52 * 0xbb000000-0xbb000fff NAND flash area buf IGNORED
53 * 0xbb001000-0xbb0011ff NAND flash reserved IGNORED
55 * 0xbb001e00-0xbb001fff NAN flash CTRL reg IGNORED
H A Dsbsa-ref.c37 #include "hw/block/flash.h"
107 PFlashCFI01 *flash[2]; member
294 * Create a single flash device. We use the same parameters as in sbsa_flash_create1()
295 * the flash devices on the Versatile Express board. in sbsa_flash_create1()
316 sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); in sbsa_flash_create()
317 sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); in sbsa_flash_create()
320 static void sbsa_flash_map1(PFlashCFI01 *flash, in sbsa_flash_map1() argument
324 DeviceState *dev = DEVICE(flash); in sbsa_flash_map1()
341 * Map two flash devices to fill the SBSA_FLASH space in the memmap. in sbsa_flash_map()
343 * of the system, and the first flash device should be made visible only in sbsa_flash_map()
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H A Dfby35.c53 error_setg(errp, "failed to get flash size"); in fby35_bmc_write_boot_rom()
63 error_setg(errp, "failed to read the initial flash content"); in fby35_bmc_write_boot_rom()
99 /* Install first FMC flash content as a boot rom. */ in fby35_bmc_init()
181 "boot directly from CE0 flash device"); in fby35_class_init()
H A Dnpcm8xx_boards.c60 DeviceState *flash; in npcm8xx_connect_flash() local
63 flash = qdev_new(flash_type); in npcm8xx_connect_flash()
65 qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo)); in npcm8xx_connect_flash()
67 qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal); in npcm8xx_connect_flash()
69 flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0); in npcm8xx_connect_flash()
H A Dstm32f205_soc.c116 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", in stm32f205_soc_realize()
119 "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f205_soc_realize()
121 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); in stm32f205_soc_realize()
/qemu/include/hw/nvram/
H A Dnrf51_nvm.h4 * It provides an interface to erase regions in flash memory.
11 * + flash-size property: flash size in bytes.
54 MemoryRegion flash; member
/qemu/docs/system/riscv/
H A Dsifive_u.rst25 * 1 ISSI 25WP256 flash
83 - start-in-flash
85 When given, QEMU's ROM codes jump to QSPI memory-mapped flash directly.
108 msel=6 means FSBL and SSBL are both on the QSPI flash. msel=11 means FSBL
226 To start U-Boot using the ``sifive_u`` machine, prepare an SPI flash image, or
255 SPI flash image has slightly different partition offsets, and the size has to
256 be 32 MiB to match the ISSI 25WP256 flash on the real board:
298 Changing msel= value to 6, allows booting U-Boot from the SPI flash:
315 case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,
320 without the needs of preparing the SPI flash or SD card images, an alternate
/qemu/tests/qtest/
H A Daspeed_smc-test.c2 * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
47 /* fmc cs0 with n25q256a flash */ in test_palmetto_bmc()
94 /* fmc cs0 with mx25l25635e flash */ in test_ast2500_evb()
137 /* fmc cs0 with mx66u51235f flash */ in test_ast2600_evb()
180 /* fmc cs0 with w25q80bl flash */ in test_ast1030_evb()
/qemu/docs/interop/
H A Dfirmware.json51 # @flash: The firmware executable and its accompanying NVRAM file are to
63 'data' : [ 'flash', 'kernel', 'memory' ] }
221 # will not use flash for nvram. When loading the
222 # firmware into flash the 'stateless' setup should be
304 # and its accompanying NVRAM file, when @FirmwareDevice is @flash.
394 'data' : { 'flash' : 'FirmwareMappingFlash',
527 # "device": "flash",
570 # "device": "flash",
614 # "device": "flash",
653 # "device": "flash",
/qemu/hw/ppc/
H A Dpnv_pnor.c68 * TODO: Check endianness: skiboot is BIG, Aspeed AHB is LITTLE, flash
96 error_setg(errp, "failed to get flash size"); in pnv_pnor_realize()
103 error_setg(errp, "failed to read the initial flash content"); in pnv_pnor_realize()
H A Dsam460ex.c30 #include "hw/block/flash.h"
92 * This first creates 1MiB of flash memory mapped at the end of in sam460ex_load_uboot()
95 * If_PFLASH unit 0 is defined, the flash memory is initialized in sam460ex_load_uboot()
104 * The physical hardware appears to have 512KiB flash memory. in sam460ex_load_uboot()
113 "sam460ex.flash", FLASH_SIZE, in sam460ex_load_uboot()
116 error_report("Error registering flash memory"); in sam460ex_load_uboot()
122 /*error_report("No flash image given with the 'pflash' parameter," in sam460ex_load_uboot()
225 * On reset the flash is mapped by a shadow TLB, but since we in main_cpu_reset()

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