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/linux-5.10/arch/powerpc/kvm/
Dbook3s_xive_template.c77 /* If the XIVE supports the new "store EOI facility, use it */ in GLUE()
84 * For LSIs the HW EOI cycle is used rather than PQ bits, in GLUE()
93 * Otherwise for EOI, we use the special MMIO that does in GLUE()
95 * except for LSIs where we use the "EOI cycle" special in GLUE()
148 * Snapshot the queue page. The test further down for EOI in GLUE()
151 * to miss an EOI. in GLUE()
165 * we EOI it now, thus re-enabling reception of a new in GLUE()
240 * If this is an EOI that's it, no CPPR adjustment done here, in GLUE()
427 /* If it's not an LSI, set PQ to 11 the EOI will force a resend */ in GLUE()
431 /* EOI the source */ in GLUE()
[all …]
Dbook3s_hv_rm_xics.c687 * ICS EOI handling: For LSI, if P bit is still set, we need to in ics_rm_eoi()
745 * ICP State: EOI in xics_rm_h_eoi()
747 * Note: If EOI is incorrectly used by SW to lower the CPPR in xics_rm_h_eoi()
752 * The sending of an EOI to the ICS is handled after the in xics_rm_h_eoi()
760 /* IPIs have no EOI */ in xics_rm_h_eoi()
789 /* EOI it */ in icp_eoi()
889 /* EOI the interrupt */ in kvmppc_deliver_irq_passthru()
/linux-5.10/arch/powerpc/sysdev/xics/
Dicp-opal.c32 * We take the ipi irq but and never return so we need to EOI the IPI, in icp_opal_flush_ipi()
81 /* We might learn about it later, so EOI it */ in icp_opal_get_irq()
114 * EOI tells us whether there are more interrupts to fetch. in icp_opal_eoi()
168 /* EOI the interrupt */ in icp_opal_flush_interrupt()
176 .eoi = icp_opal_eoi,
Dicp-hv.c52 pr_err("%s: bad return code eoi xirr=0x%x returned %ld\n", in icp_hv_set_xirr()
93 * need to EOI the IPI, but want to leave our priority 0 in icp_hv_flush_ipi()
121 /* We might learn about it later, so EOI it */ in icp_hv_get_irq()
154 .eoi = icp_hv_eoi,
Dicp-native.c105 * need to EOI the IPI, but want to leave our priority 0 in icp_native_flush_ipi()
133 /* We might learn about it later, so EOI it */ in icp_native_get_irq()
189 /* EOI the interrupt */ in icp_native_flush_interrupt()
317 .eoi = icp_native_eoi,
/linux-5.10/drivers/xen/events/
Devents_base.c103 unsigned short eoi_cpu; /* EOI must happen on this cpu-1 */
105 u64 eoi_time; /* Time in jiffies when to EOI. */
477 struct lateeoi_work *eoi = &per_cpu(lateeoi, info->eoi_cpu); in lateeoi_list_del() local
480 spin_lock_irqsave(&eoi->eoi_list_lock, flags); in lateeoi_list_del()
482 spin_unlock_irqrestore(&eoi->eoi_list_lock, flags); in lateeoi_list_del()
487 struct lateeoi_work *eoi = &per_cpu(lateeoi, info->eoi_cpu); in lateeoi_list_add() local
498 spin_lock_irqsave(&eoi->eoi_list_lock, flags); in lateeoi_list_add()
500 if (list_empty(&eoi->eoi_list)) { in lateeoi_list_add()
501 list_add(&info->eoi_list, &eoi->eoi_list); in lateeoi_list_add()
503 &eoi->delayed, delay); in lateeoi_list_add()
[all …]
/linux-5.10/drivers/xen/xen-pciback/
Dpciback_ops.c295 bool eoi = true; in xen_pcibk_test_and_schedule_op() local
301 eoi = false; in xen_pcibk_test_and_schedule_op()
308 eoi = false; in xen_pcibk_test_and_schedule_op()
311 /* EOI if there was nothing to do. */ in xen_pcibk_test_and_schedule_op()
312 if (eoi) in xen_pcibk_test_and_schedule_op()
412 bool eoi; in xen_pcibk_handle_event() local
418 eoi = test_and_set_bit(_EOI_pending, &pdev->flags); in xen_pcibk_handle_event()
419 WARN(eoi, "IRQ while EOI pending\n"); in xen_pcibk_handle_event()
/linux-5.10/drivers/irqchip/
Dirq-i8259.c131 * first, _then_ send the EOI, and the order of EOI
164 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ in mask_and_ack_8259A()
165 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ in mask_and_ack_8259A()
169 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ in mask_and_ack_8259A()
245 if (auto_eoi) /* master does Auto EOI */ in init_8259A()
247 else /* master expects normal EOI */ in init_8259A()
Dirq-clps711x.c40 phys_addr_t eoi; member
95 writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hwirq].eoi); in clps711x_intc_eoi()
139 } else if (clps711x_irqs[hw].eoi) { in clps711x_intc_irq_map()
144 if (clps711x_irqs[hw].eoi) in clps711x_intc_irq_map()
145 writel_relaxed(0, clps711x_intc->base + clps711x_irqs[hw].eoi); in clps711x_intc_irq_map()
/linux-5.10/arch/x86/kvm/
Dioapic.c199 * If no longer has pending EOI in LAPICs, update in ioapic_lazy_update_eoi()
200 * EOI for this vector. in ioapic_lazy_update_eoi()
225 * AMD SVM AVIC accelerate EOI write iff the interrupt is edge in ioapic_set_irq()
227 * to receive the EOI. In this case, we do a lazy update of the in ioapic_set_irq()
228 * pending EOI when trying to set IOAPIC irq. in ioapic_set_irq()
237 * us if the interrupt is waiting for an EOI. in ioapic_set_irq()
240 * if it has been already ack-ed via EOI because coalesced RTC in ioapic_set_irq()
242 * EOI manually for the RTC interrupt. in ioapic_set_irq()
288 /* Make sure we see any missing RTC EOI */ in kvm_ioapic_scan_entry()
364 * explicit EOI on IOAPICs that don't have the EOI register. in ioapic_write_indirect()
[all …]
Dlapic.c370 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with in kvm_apic_set_version()
371 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC in kvm_apic_set_version()
673 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n", in pv_eoi_get_pending()
683 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n", in pv_eoi_set_pending()
693 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n", in pv_eoi_clr_pending()
1213 /* Eoi the ioapic only if the ioapic doesn't own the vector. */ in kvm_ioapic_send_eoi()
1239 * Not every write EOI will has corresponding ISR, in apic_set_eoi()
2517 * For auto-EOI interrupts, there might be another pending in kvm_get_apic_interrupt()
2635 * Detect whether guest triggered PV EOI since the
2636 * last entry. If yes, set EOI on guests's behalf.
[all …]
/linux-5.10/arch/powerpc/sysdev/xive/
Dcommon.c309 * as a "replay" because EOI decided there was still something in xive_get_irq()
317 * entry (on HW interrupt) from a replay triggered by EOI, in xive_get_irq()
338 * After EOI'ing an interrupt, we need to re-check the queue
350 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio); in xive_do_queue_eoi()
356 * EOI an interrupt at the source. There are several methods
362 /* If the XIVE supports the new "store EOI facility, use it */ in xive_do_source_eoi()
373 if (WARN_ON_ONCE(!xive_ops->eoi)) in xive_do_source_eoi()
375 xive_ops->eoi(hw_irq); in xive_do_source_eoi()
380 * Otherwise for EOI, we use the special MMIO that does in xive_do_source_eoi()
382 * except for LSIs where we use the "EOI cycle" special in xive_do_source_eoi()
[all …]
/linux-5.10/arch/x86/kernel/
Di8259.c147 * first, _then_ send the EOI, and the order of EOI
180 /* 'Specific EOI' to slave */ in mask_and_ack_8259A()
182 /* 'Specific EOI' to master-IRQ2 */ in mask_and_ack_8259A()
187 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ in mask_and_ack_8259A()
348 if (auto_eoi) /* master does Auto EOI */ in init_8259A()
350 else /* master expects normal EOI */ in init_8259A()
/linux-5.10/Documentation/virt/kvm/
Dmsr.rst319 injection. Value of 1 means that guest can skip writing EOI to the apic
321 EOI by clearing the bit in guest memory - this location will
323 Value of 0 means that the EOI write is required.
326 the APIC EOI write anyway.
337 whether it can skip EOI apic write and between guest
338 clearing it to signal EOI to the hypervisor,
/linux-5.10/arch/x86/kernel/cpu/
Dacrn.c43 * The hypervisor requires that the APIC EOI should be acked. in DEFINE_IDTENTRY_SYSVEC()
44 * If the APIC EOI is not acked, the APIC ISR bit for the in DEFINE_IDTENTRY_SYSVEC()
/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmstar,mst-intc.yaml42 mstar,intc-no-eoi:
44 Mark this controller has no End Of Interrupt(EOI) implementation.
/linux-5.10/arch/powerpc/include/asm/
Dxive-regs.h14 * to a queue and is waiting for an EOI). Q indicates that the
20 * When doing an EOI, the Q bit will indicate if the interrupt
28 * Additionally, some ESB pages support doing an EOI via a
/linux-5.10/arch/mips/sibyte/sb1250/
Dirq.c161 * Generate EOI. For Pass 1 parts, EOI is a nop. For in ack_sb1250_irq()
163 * this EOI shouldn't hurt. If they are in ack_sb1250_irq()
164 * level-sensitive, the EOI is required. in ack_sb1250_irq()
/linux-5.10/Documentation/core-api/
Dgenericirq.rst44 - Fast EOI type
235 Default Fast EOI IRQ flow handler
239 which only need an EOI at the end of the handler.
304 EOI Edge IRQ flow handler
359 - ``irq_eoi`` - Optional, required for EOI flow handlers
/linux-5.10/drivers/hid/intel-ish-hid/ishtp/
Dclient.c830 goto eoi; in recv_ishtp_cl_msg()
836 goto eoi; in recv_ishtp_cl_msg()
857 goto eoi; in recv_ishtp_cl_msg()
875 goto eoi; in recv_ishtp_cl_msg()
928 goto eoi; in recv_ishtp_cl_msg()
937 eoi: in recv_ishtp_cl_msg()
979 goto eoi; in recv_ishtp_cl_msg_dma()
996 goto eoi; in recv_ishtp_cl_msg_dma()
1045 goto eoi; in recv_ishtp_cl_msg_dma()
1054 eoi: in recv_ishtp_cl_msg_dma()
/linux-5.10/arch/m68k/atari/
Dataints.c276 st_mfp.vec_adr = 0x48; /* Software EOI-Mode */ in atari_init_IRQ()
278 st_mfp.vec_adr = 0x40; /* Automatic EOI-Mode */ in atari_init_IRQ()
287 tt_mfp.vec_adr = 0x58; /* Software EOI-Mode */ in atari_init_IRQ()
289 tt_mfp.vec_adr = 0x50; /* Automatic EOI-Mode */ in atari_init_IRQ()
/linux-5.10/arch/mips/sibyte/bcm1480/
Dirq.c176 * Generate EOI. For Pass 1 parts, EOI is a nop. For in ack_bcm1480_irq()
178 * this EOI shouldn't hurt. If they are in ack_bcm1480_irq()
179 * level-sensitive, the EOI is required. in ack_bcm1480_irq()
/linux-5.10/drivers/media/platform/mtk-jpeg/
Dmtk_jpeg_dec_parse.c17 #define EOI 0xd9 macro
128 case EOI: in mtk_jpeg_do_parse()
/linux-5.10/arch/parisc/include/asm/
Dsuperio.h34 #define OCW2_EOI 0x20 /* Non-specific EOI */
35 #define OCW2_SEOI 0x60 /* Specific EOI */
/linux-5.10/arch/powerpc/sysdev/
Di8259.c85 outb(0x20, 0xA0); /* Non-specific EOI */ in i8259_mask_and_ack_irq()
86 outb(0x20, 0x20); /* Non-specific EOI to cascade */ in i8259_mask_and_ack_irq()
91 outb(0x20, 0x20); /* Non-specific EOI */ in i8259_mask_and_ack_irq()

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