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Searched full:emc_fbio_cfg5 (Results 1 – 12 of 12) sorted by relevance

/linux-5.10/arch/arm/boot/dts/
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi369 0x00004288 /* EMC_FBIO_CFG5 */
473 0x00004288 /* EMC_FBIO_CFG5 */
577 0x00004288 /* EMC_FBIO_CFG5 */
681 0x00004288 /* EMC_FBIO_CFG5 */
783 0x00007088 /* EMC_FBIO_CFG5 */
886 0x00005088 /* EMC_FBIO_CFG5 */
994 0x00004288 /* EMC_FBIO_CFG5 */
1098 0x00004288 /* EMC_FBIO_CFG5 */
1202 0x00004288 /* EMC_FBIO_CFG5 */
1306 0x00004288 /* EMC_FBIO_CFG5 */
[all …]
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi64 0x00005088 /* EMC_FBIO_CFG5 */
168 0x00007088 /* EMC_FBIO_CFG5 */
271 0x00005088 /* EMC_FBIO_CFG5 */
Dtegra124-nyan-big-emc.dtsi301 0x106aa298 /* EMC_FBIO_CFG5 */
469 0x106aa298 /* EMC_FBIO_CFG5 */
637 0x106aa298 /* EMC_FBIO_CFG5 */
805 0x106aa298 /* EMC_FBIO_CFG5 */
973 0x106aa298 /* EMC_FBIO_CFG5 */
1141 0x106aa298 /* EMC_FBIO_CFG5 */
1309 0x104ab098 /* EMC_FBIO_CFG5 */
1477 0x104ab098 /* EMC_FBIO_CFG5 */
1645 0x104ab098 /* EMC_FBIO_CFG5 */
1813 0x104ab098 /* EMC_FBIO_CFG5 */
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml144 - description: EMC_FBIO_CFG5
283 0x00005088 /* EMC_FBIO_CFG5 */
Dnvidia,tegra124-emc.yaml210 - description: EMC_FBIO_CFG5
436 0x106aa298 /* EMC_FBIO_CFG5 */
/linux-5.10/drivers/memory/tegra/
Dtegra210-emc-core.c162 EMC_FBIO_CFG5,
1314 EMC_FBIO_CFG5, (100000 / clk) + 10); in tegra210_emc_dvfs_power_ramp_up()
1320 EMC_FBIO_CFG5, (100000 / clk) + 10); in tegra210_emc_dvfs_power_ramp_up()
1326 EMC_FBIO_CFG5, 12); in tegra210_emc_dvfs_power_ramp_up()
1358 EMC_FBIO_CFG5, 12); in tegra210_emc_dvfs_power_ramp_down()
1790 value = emc_readl(emc, EMC_FBIO_CFG5); in tegra210_emc_detect()
Dtegra30-emc.c81 #define EMC_FBIO_CFG5 0x104 macro
260 [39] = EMC_FBIO_CFG5,
530 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_prepare_timing_change()
1013 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
Dtegra124-emc.c25 #define EMC_FBIO_CFG5 0x104 macro
347 EMC_FBIO_CFG5,
871 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
Dtegra20-emc.c63 #define EMC_FBIO_CFG5 0x104 macro
128 EMC_FBIO_CFG5,
Dtegra210-emc.h104 #define EMC_FBIO_CFG5 0x104 macro
Dtegra210-emc-cc-r21021.c630 value = emc_readl(emc, EMC_FBIO_CFG5) & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in tegra210_emc_r21021_set_clock()
/linux-5.10/arch/arm/mach-tegra/
Dsleep-tegra30.S24 #define EMC_FBIO_CFG5 0x104 macro
478 ldr r2, [r0, #EMC_FBIO_CFG5]