Searched full:emc_cfg_2 (Results 1 – 6 of 6) sorted by relevance
| /linux-5.10/drivers/memory/tegra/ |
| D | tegra124-emc.c | 130 #define EMC_CFG_2 0x2b8 macro
450 u32 emc_cfg_2; member
716 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
718 emc_ccfifo_writel(emc, val, EMC_CFG_2); in tegra_emc_prepare_timing_change()
781 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
782 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
923 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") in load_one_timing_from_dt()
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| D | tegra20-emc.c | 66 #define EMC_CFG_2 0x2b8 macro
413 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
428 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
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| D | tegra210-emc.h | 140 #define EMC_CFG_2 0x2b8 macro
866 u32 emc_cfg_2; member
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| D | tegra30-emc.c | 88 #define EMC_CFG_2 0x2b8 macro
1016 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1034 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
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| D | tegra210-emc-cc-r21021.c | 866 emc_writel(emc, next->emc_cfg_2, EMC_CFG_2); in tegra210_emc_r21021_set_clock()
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 95 value of the EMC_CFG_2 register for this set of timings
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