| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | hisilicon,hi3660-usb3.yaml | 29 hisilicon,eye-diagram-param:
32 description: Eye diagram for phy.
38 - hisilicon,eye-diagram-param
50 hisilicon,eye-diagram-param = <0x22466e4>;
|
| H A D | hisilicon,hi3670-usb3.yaml | 34 hisilicon,eye-diagram-param:
37 description: Eye diagram for phy.
48 - hisilicon,eye-diagram-param
62 hisilicon,eye-diagram-param = <0xfdfee4>;
|
| H A D | hisilicon,phy-hi3670-pcie.yaml | 45 hisilicon,eye-diagram-param:
47 description: Eye diagram for phy.
55 - hisilicon,eye-diagram-param
79 hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
|
| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | programming-model-dcn.rst | 62 The diagram below provides an overview of the display driver architecture;
67 The first layer of the diagram is the high-level DC API represented by the
73 DPP, MPC, OPTC, etc. Notice on the left side of the diagram that we have a
80 The below diagram outlines the basic display objects. In particular, pay
91 After the `dc` block in the diagram, you can see the `dc_link` component, which
105 There are two structs that are not represented in the diagram since they were
106 elaborated in the DCN overview page (check the DCN block diagram :ref:`Display
115 Speaking of the `dc_plane` data structure (first part of the diagram), you can
|
| H A D | dcn-overview.rst | 10 generic diagram, and we have variations per ASIC.
14 Based on this diagram, we can pass through each block and briefly describe
53 The above diagram is an architecture generalization of DCN, which means that
64 sophisticated communication interface which is highlighted in the diagram by
160 The first thing to notice from the diagram and DTN log it is the fact that we
164 we can split this single pipe differently, as described in the below diagram:
|
| /linux/Documentation/devicetree/bindings/display/panel/ |
| H A D | panel-edp.yaml | 37 vast majority of panel datasheets have a power sequence diagram that
39 cares about different timings in this diagram but the fact that the
40 diagram is so similar means we can come up with a single driver to
45 sequence. This is because much of this diagram comes straight from
102 from power on (timing T3 in the diagram above). If we have no way to
|
| /linux/Documentation/RCU/Design/Memory-Ordering/ |
| H A D | Tree-RCU-Memory-Ordering.rst | 286 diagram above.
360 The diagram below shows the path of ordering if the leftmost
371 in the following diagram.
411 following diagram:
426 diagram happens after the start of the grace period. In addition, this
463 diagram, clearing bits from each ``rcu_node`` structure's ``->qsmask``
493 precede the idle period (the oval near the top of the diagram above)
497 the bottom of the diagram above).
556 | RCU. But this diagram is complex enough as it is, so simplicity |
559 | `stitched-together diagram <Putting It All Together_>`__. |
[all …]
|
| /linux/drivers/clk/rockchip/ |
| H A D | clk-rv1126.c | 269 * Clock-Architecture Diagram 2
392 * Clock-Architecture Diagram 1
399 * Clock-Architecture Diagram 3
416 * Clock-Architecture Diagram 4
626 * Clock-Architecture Diagram 6
723 * Clock-Architecture Diagram 9
766 * Clock-Architecture Diagram 12
888 * Clock-Architecture Diagram 15
904 * Clock-Architecture Diagram 3
919 * Clock-Architecture Diagram 4
[all …]
|
| H A D | clk-rk3328.c | 266 * Clock-Architecture Diagram 1
282 * Clock-Architecture Diagram 2
345 * Clock-Architecture Diagram 3
438 * Clock-Architecture Diagram 4
496 * Clock-Architecture Diagram 5
565 * Clock-Architecture Diagram 6
602 * Clock-Architecture Diagram 7
654 * Clock-Architecture Diagram 8
700 * Clock-Architecture Diagram 9
|
| H A D | clk-px30.c | 266 * Clock-Architecture Diagram 1
274 * Clock-Architecture Diagram 3
328 * Clock-Architecture Diagram 4
380 * Clock-Architecture Diagram 5
402 * Clock-Architecture Diagram 6
453 * Clock-Architecture Diagram 7
570 * Clock-Architecture Diagram 8
793 * Clock-Architecture Diagram 9
916 * Clock-Architecture Diagram 2
966 * Clock-Architecture Diagram 9
|
| H A D | clk-rk3308.c | 281 * Clock-Architecture Diagram 1
289 * Clock-Architecture Diagram 2
312 * Clock-Architecture Diagram 3
461 * Clock-Architecture Diagram 4
549 * Clock-Architecture Diagram 5
576 * Clock-Architecture Diagram 6
618 * Clock-Architecture Diagram 7
806 * Clock-Architecture Diagram 8
|
| /linux/Documentation/driver-api/pldmfw/ |
| H A D | file-format.rst | 12 This diagram provides an overview of the file format::
57 The following diagram provides an overview of the package header::
90 The following diagram provides an overview of the device record area::
145 The following diagram provides an overview of the component area::
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | hisilicon-hns-nic.txt | 17 port-id can be 2 to 7. Here is the diagram:
44 to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram:
|
| /linux/Documentation/driver-api/ |
| H A D | interconnect.rst | 22 Below is a simplified diagram of a real-world SoC interconnect bus topology.
56 The interconnect providers on the above diagram are M NoC, S NoC, C NoC, P NoC
62 providers. The point on the diagram where the CPUs connect to the memory is
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | starfive,jh7100-pinctrl.yaml | 15 interesting 2-layered approach to pin muxing best illustrated by the diagram
36 The big MUX in the diagram only has 7 different ways of mapping peripherals
40 diagram only shows UART0 and UART1, but this also includes a number of other
|
| /linux/Documentation/core-api/ |
| H A D | list.rst | 147 This diagram shows the singular "clowns" node pointing at itself. In this
148 diagram, and all following diagrams, only the forward edges are shown, to aid in
159 This diagram shows the "clowns" node pointing at a new node labeled "Grock".
170 This diagram shows the "clowns" node pointing at a new node labeled "Dimitri",
198 This diagram shows the "clowns" node pointing at the node labeled "Grock",
293 This diagram shows the "clowns" node pointing at the node labeled "Grock",
328 This diagram shows the "clowns" node pointing at the node labeled "Grock",
560 in the following diagram::
732 somewhat surprising diagram of the resulting "State 1" follows::
|
| /linux/Documentation/scsi/scsi_transport_srp/ |
| H A D | figures.rst | 3 SCSI RDMA (SRP) transport class diagram
|
| /linux/Documentation/devicetree/bindings/net/wireless/ |
| H A D | qcom,ath12k-wsi.yaml | 25 Diagram to represent one WSI connection (one WSI group) among
36 Diagram to represent two WSI connections (two separate WSI groups)
|
| /linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| H A D | overview.rst | 31 The diagram below shows an overview of the DPAA2 resource management
84 types of DPAA2 objects. In the example diagram below there
144 The diagram below shows the objects needed for a simple
284 The diagram below shows the Linux drivers involved in a networking
|
| /linux/Documentation/devicetree/bindings/soc/hisilicon/ |
| H A D | hisilicon,hi3660-usb3-otg-bc.yaml | 44 hisilicon,eye-diagram-param = <0x22466e4>;
|
| /linux/drivers/gpu/drm/bridge/ |
| H A D | simple-bridge.c | 232 /* From timing diagram, datasheet page 9 */
245 /* From timing diagram, datasheet page 14 */
|
| /linux/Documentation/PCI/endpoint/ |
| H A D | pci-ntb-function.rst | 20 In the below diagram, PCI NTB function configures the SoC with multiple
291 Above diagram shows Config region + Scratchpad region for HOST1 (connected to
296 diagram shows the case where Config region and Scratchpad regions are allocated
335 Above diagram shows how the doorbell and memory window 1 is mapped so that
|
| /linux/Documentation/edac/ |
| H A D | features.rst | 31 High level design is illustrated in the following diagram::
84 example: scrub, ECS, memory repair in the above diagram.
|
| /linux/drivers/interconnect/imx/ |
| H A D | imx8mn.c | 29 * This is a simplified subset of the bus diagram, there are several other
|
| /linux/Documentation/infiniband/ |
| H A D | opa_vnic.rst | 23 different virtual Ethernet switch. The below diagram presents a case
103 Intel OPA VNIC software design is presented in the below diagram.
|