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/linux-5.10/drivers/dma/xilinx/
Dxilinx_dpdma.c3 * Xilinx ZynqMP DPDMA Engine driver
27 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
32 /* DPDMA registers */
117 /* DPDMA descriptor fields */
140 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
178 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
179 * @hw: DPDMA hardware descriptor
190 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor
207 * struct xilinx_dpdma_chan - DPDMA channel
221 * @xdev: DPDMA device
[all …]
/linux-5.10/Documentation/devicetree/bindings/dma/xilinx/
Dxlnx,zynqmp-dpdma.yaml4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
29 const: xlnx,zynqmp-dpdma
59 compatible = "xlnx,zynqmp-dpdma";
/linux-5.10/drivers/gpu/drm/xlnx/
Dzynqmp_disp.h24 /* The DPDMA is limited to 44 bit addressing. */
Dzynqmp_disp.c50 * | DPDMA | --->| | --> | Video | Video +-------------+ |
64 * Only non-live input from the DPDMA and output to the DisplayPort Source
68 * The display controller code creates planes for the DPDMA video and graphics
/linux-5.10/Documentation/devicetree/bindings/display/xlnx/
Dxlnx,zynqmp-dpsub.yaml16 | DPDMA | --->| | --> | Video | Video +-------------+ |
/linux-5.10/drivers/dma/
DKconfig694 tristate "Xilinx DPDMA Engine"
/linux-5.10/
DMAINTAINERS19302 XILINX ZYNQMP DPDMA DRIVER
19307 F: Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
19309 F: include/dt-bindings/dma/xlnx-zynqmp-dpdma.h