| /linux-5.10/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 31 * R0 : DLL ctrl value pre-Sleep
36 * when we get called, but the DLL probably isn't. We will wait a bit more in
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
48 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
|
| D | sram243x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
|
| D | sram242x.S | 45 /* dll lock mode */
52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
55 bl i_dll_wait @ wait for dll to lock
57 /* get dll value */
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
[all …]
|
| D | sdrc2xxx.c | 32 /* Memory timing, DLL mode flags */
58 * Check the DLL lock state, and return tue if running in unlock mode.
59 * This is needed to compensate for the shifted DLL value in unlock mode.
133 /* With DDR we need to determine the low frequency DLL value */ in omap2xxx_sdrc_init_params()
150 /* set fast timings with DLL filter disabled */ in omap2xxx_sdrc_init_params()
164 /* 90 degree phase for anything below 133MHz + disable DLL filter */ in omap2xxx_sdrc_init_params()
|
| D | sdrc.h | 92 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
93 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
114 /* Minimum frequency that the SDRC DLL can lock at */
|
| /linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | cdns,sdhci.yaml | 32 # PHY DLL input delays:
82 # PHY DLL clock delays:
90 cdns,phy-dll-delay-sdclk:
98 cdns,phy-dll-delay-sdclk-hsmmc:
106 cdns,phy-dll-delay-strobe:
133 cdns,phy-dll-delay-sdclk = <0>;
|
| D | fsl-imx-esdhc.yaml | 60 This is used to set the clock delay for DLL(Delay Line) on override mode
63 chapter, DLL (Delay Line) section in RM for details.
95 fsl,strobe-dll-delay-target:
98 Specify the strobe dll control slave delay target.
|
| D | sdhci-msm.txt | 54 - qcom,dll-config: Chipset and Platform specific value. Use this field to
93 qcom,dll-config = <0x000f642c>;
113 qcom,dll-config = <0x0007642c>;
|
| /linux-5.10/arch/x86/boot/ |
| D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
104 unsigned char lcr, dll, dlh; in probe_baud() local
109 dll = inb(port + DLL); in probe_baud()
112 quot = (dlh << 8) | dll; in probe_baud()
|
| /linux-5.10/arch/powerpc/kernel/ |
| D | udbg_16550.c | 97 unsigned int dll, base_bauds; in udbg_uart_setup() local
108 dll = base_bauds / speed; in udbg_uart_setup()
114 udbg_uart_out(UART_DLL, dll & 0xff); in udbg_uart_setup()
115 udbg_uart_out(UART_DLM, dll >> 8); in udbg_uart_setup()
126 unsigned int dll, dlm, divisor, prescaler, speed; in udbg_probe_uart_speed() local
135 dll = udbg_uart_in(UART_DLL); in udbg_probe_uart_speed()
137 divisor = dlm << 8 | dll; in udbg_probe_uart_speed()
|
| /linux-5.10/drivers/phy/intel/ |
| D | phy-intel-keembay-emmc.c | 76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
130 /* Set the frequency of the DLL operation */ in keembay_emmc_phy_power()
134 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in keembay_emmc_phy_power()
138 /* Turn on the DLL */ in keembay_emmc_phy_power()
142 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in keembay_emmc_phy_power()
147 * We turned on the DLL even though the rate was 0 because we the in keembay_emmc_phy_power()
148 * clock might be turned on later. ...but we can't wait for the DLL in keembay_emmc_phy_power()
159 * After enabling analog DLL circuits docs say that we need 10.2 us if in keembay_emmc_phy_power()
167 * NOTE: There appear to be corner cases where the DLL seems to take in keembay_emmc_phy_power()
|
| D | phy-intel-lgm-emmc.c | 110 /* Set the frequency of the DLL operation */ in intel_emmc_phy_power()
114 dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret); in intel_emmc_phy_power()
118 /* Turn on the DLL */ in intel_emmc_phy_power()
122 dev_err(&phy->dev, "turn on the dll failed: %d\n", ret); in intel_emmc_phy_power()
127 * After enabling analog DLL circuits docs say that we need 10.2 us if in intel_emmc_phy_power()
135 * NOTE: There appear to be corner cases where the DLL seems to take in intel_emmc_phy_power()
|
| /linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 62 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
64 DDR3 DLL will be bypassed. Note: if DLL was bypassed,
67 - rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
69 DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
70 Note: PHY DLL and PHY ODT are independent.
|
| /linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-emmc.c | 142 * pretty spot on for the DLL range, so warn if we're too in rockchip_emmc_phy_power()
178 /* Set the frequency of the DLL operation */ in rockchip_emmc_phy_power()
184 /* Turn on the DLL */ in rockchip_emmc_phy_power()
192 * We turned on the DLL even though the rate was 0 because we the in rockchip_emmc_phy_power()
193 * clock might be turned on later. ...but we can't wait for the DLL in rockchip_emmc_phy_power()
204 * After enabling analog DLL circuits docs say that we need 10.2 us if in rockchip_emmc_phy_power()
212 * NOTE: There appear to be corner cases where the DLL seems to take in rockchip_emmc_phy_power()
|
| /linux-5.10/drivers/mmc/host/ |
| D | sdhci-esdhc.h | 89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
|
| D | sdhci-msm.c | 429 * Write the selected DLL clock output phase (0 ... 15) in msm_config_cm_dll_phase()
453 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", in msm_config_cm_dll_phase()
462 * DLL clock output phases that can be used as sampling
466 * Select the 3/4 of the range and configure the DLL with the
467 * selected DLL clock output phase.
602 /* Initialize the DLL (Programmable Delay Line) */
620 * Make sure that clock is always enabled when DLL in msm_init_cm_dll()
682 /* wait for 5us before enabling DLL clock */ in msm_init_cm_dll()
709 * Configure DLL user control register to enable DLL status. in msm_init_cm_dll()
746 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", in msm_init_cm_dll()
[all …]
|
| D | sdhci-pci-o2micro.c | 172 * This function is used to detect dll lock status.
173 * Since the dll lock status bit will toggle randomly
223 * This function is used to fix o2 dll shift issue.
266 * need wait at least 5ms for dll status stable, in sdhci_o2_dll_recovery()
276 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n", in sdhci_o2_dll_recovery()
289 pr_err("%s: DLL adjust over max times\n", in sdhci_o2_dll_recovery()
316 * Judge the tuning reason, whether caused by dll shift in sdhci_o2_execute_tuning()
317 * If cause by dll shift, should call sdhci_o2_dll_recovery in sdhci_o2_execute_tuning()
321 pr_err("%s: o2 dll recovery failed\n", in sdhci_o2_execute_tuning()
422 /* Set DLL Tuning Window */ in sdhci_pci_o2_fujin2_pci_init()
[all …]
|
| D | sdhci-xenon-phy.c | 125 /* Offset of DLL Control register */
129 /* DLL Update Enable bit */
316 * Enable eMMC PHY HW DLL
317 * DLL should be enabled and stable before HS200/SDR104 tuning,
335 /* Enable DLL */ in xenon_emmc_phy_enable_dll()
364 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); in xenon_emmc_phy_enable_dll()
374 * Enable HW DLL and set the TUNING_STEP
391 /* Achieve TUNING_STEP with HW DLL help */ in xenon_emmc_phy_config_tuning()
461 * 3. DLL is enabled in xenon_emmc_phy_strobe_delay_adj()
|
| D | sdhci_am654.c | 189 /* Configure PHY DLL frequency */ in sdhci_am654_setup_dll()
206 /* Configure DLL TRIM */ in sdhci_am654_setup_dll()
210 /* Configure DLL driver strength */ in sdhci_am654_setup_dll()
215 /* Enable DLL */ in sdhci_am654_setup_dll()
219 * Poll for DLL ready. Use a one second timeout. in sdhci_am654_setup_dll()
225 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); in sdhci_am654_setup_dll()
269 /* Setup DLL Output TAP delay */ in sdhci_am654_set_clock()
311 /* Setup DLL Output TAP delay */ in sdhci_j721e_4bit_set_clock()
|
| /linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
|
| D | sddr2.c | 63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
|
| D | sddr3.c | 72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
|
| /linux-5.10/drivers/tty/serial/8250/ |
| D | 8250_pxa.c | 66 unsigned int dll; in serial_pxa_dl_write() local
73 dll = serial_in(up, UART_DLL); in serial_pxa_dl_write()
74 WARN_ON(dll != (value & 0xff)); in serial_pxa_dl_write()
|
| /linux-5.10/drivers/net/ethernet/cavium/thunder/ |
| D | thunder_xcv.c | 69 /* Take DLL out of reset */ in xcv_init_hw()
78 /* Wait for DLL to lock */ in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
|
| /linux-5.10/include/soc/at91/ |
| D | at91sam9_ddrsdr.h | 43 #define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
45 #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
103 #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|