| /linux-5.10/arch/arm/mach-davinci/ |
| D | sleep.S | 12 #include "ddr2.h"
34 * r0: contains virtual base for DDR2 controller
35 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
36 * r2: contains PSC number for DDR2
37 * r3: contains virtual base DDR2 PLL controller
66 /* Disable DDR2 LPSC */
138 /* Start 2x clock to DDR2 */
146 /* Enable DDR2 LPSC */
168 * Disables or Enables DDR2 LPSC
171 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
[all …]
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| D | cpuidle.c | 20 #include "ddr2.h"
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| /linux-5.10/arch/mips/ralink/ |
| D | rt3883.c | 68 u32 ddr2; in ralink_clk_init() local
73 ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; in ralink_clk_init()
78 sys_rate = (ddr2) ? 125000000 : 83000000; in ralink_clk_init()
82 sys_rate = (ddr2) ? 128000000 : 96000000; in ralink_clk_init()
86 sys_rate = (ddr2) ? 160000000 : 120000000; in ralink_clk_init()
90 sys_rate = (ddr2) ? 166000000 : 125000000; in ralink_clk_init()
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| /linux-5.10/drivers/edac/ |
| D | ppc4xx_edac.c | 24 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
29 * - Support for registered- and non-registered DDR1 and DDR2 memory.
85 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
139 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
193 .compatible = "ibm,sdram-4xx-ddr2"
657 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
685 * ibm,sdram-4xx-ddr2 ECC errors.
708 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
739 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
765 * associated with the ibm,sdram-4xx-ddr2 controller being
[all …]
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| D | ppc4xx_edac.h | 7 * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP,
24 * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those
114 #define SDRAM_MCOPT1_DDR2_TYPE PPC_REG_VAL(11, 0x1) /* DDR2 type */
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-da8xx-ddrctl.txt | 1 * Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller
3 The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | brcm,bcm2835-cprman.txt | 26 - DSI0 DDR2 clock
29 - DSI1 DDR2 clock
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| /linux-5.10/drivers/memory/ |
| D | Kconfig | 99 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
184 bool "Texas Instruments da8xx DDR2/mDDR driver"
187 This driver is for the DDR2/mDDR Memory Controller present on
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| D | da8xx-ddrctl.c | 3 * TI da8xx DDR2/mDDR controller driver
167 MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
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| D | ti-emif-sram-pm.S | 233 * disabled for DDR2 no harm in restoring the
239 /* Write to sdcfg last for DDR2 only */
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| /linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | sddr2.c | 47 /* The following are available in some, but not all DDR2 docs */
55 /* The following are available in some, but not all DDR2 docs */
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| /linux-5.10/include/linux/ |
| D | edac.h | 161 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
164 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
168 * @MEM_RDDR2: Registered DDR2 RAM
169 * This is a variant of the DDR2 memories.
172 * created to compete with DDR2. Weren't used on any
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| /linux-5.10/arch/mips/pic32/ |
| D | Kconfig | 29 internally packaged DDR2 memory up to 128MB.
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| /linux-5.10/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,hr2.yaml | 12 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
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| /linux-5.10/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca9.dts | 243 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
252 /* DDR2 SDRAM VTT termination voltage */
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| D | imx28-eukrea-mbmx287lc.dts | 8 * Module contains : i.MX287 + 128MB DDR2 + NAND + 2 x Ethernet PHY + RTC
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| D | imx28-eukrea-mbmx283lc.dts | 8 * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
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| /linux-5.10/drivers/hwmon/ |
| D | abituguru3.c | 428 { "DDR2", 1, 0, 20, 1, 0 },
429 { "DDR2 VTT", 2, 0, 10, 1, 0 },
456 { "DDR2", 1, 0, 20, 1, 0 },
457 { "DDR2 VTT", 2, 0, 10, 1, 0 },
481 { "DDR2", 1, 0, 20, 1, 0 },
482 { "DDR2 VTT", 2, 0, 10, 1, 0 },
508 { "DDR2", 13, 0, 20, 1, 0 },
509 { "DDR2 VTT", 14, 0, 10, 1, 0 },
535 { "DDR2", 1, 0, 20, 1, 0 },
536 { "DDR2 VTT", 2, 0, 10, 1, 0 },
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/display/ |
| D | brcm,bcm2835-dsi0.yaml | 43 # - description: The DSI DDR2 clock
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| /linux-5.10/Documentation/driver-api/memory-devices/ |
| D | ti-emif.rst | 30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
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| /linux-5.10/drivers/bcma/ |
| D | scan.c | 41 { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
90 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
102 { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
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| /linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | b4860si-post.dtsi | 78 dev-handle = <&ddr2>;
238 ddr2: memory-controller@9000 { label
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| /linux-5.10/drivers/i2c/ |
| D | i2c-smbus.c | 312 * - Only works for DDR2, DDR3 and DDR4 for now
365 case 0x13: /* DDR2 */ in i2c_register_spd()
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
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| /linux-5.10/arch/arm/mach-cns3xxx/ |
| D | cns3xxx.h | 15 #define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
27 #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
507 /* Change DDR2 frequency */
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