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/qemu/tests/qapi-schema/
H A Dinclude-cycle.err1 In file included from include-cycle.json:1:
2 In file included from include-cycle-b.json:1:
3 include-cycle-c.json:1: inclusion loop for include-cycle.json
H A Dinclude-self-cycle.err1 include-self-cycle.json:1: inclusion loop for include-self-cycle.json
H A Dbase-cycle-indirect.err1 base-cycle-indirect.json: In struct 'Base1':
2 base-cycle-indirect.json:2: object Base1 contains itself
H A Dbase-cycle-direct.err1 base-cycle-direct.json: In struct 'Loopy':
2 base-cycle-direct.json:2: object Loopy contains itself
H A Dmeson.build53 'base-cycle-direct.json',
54 'base-cycle-indirect.json',
121 'include-cycle.json',
127 'include-self-cycle.json',
H A Dinclude-cycle-c.json1 { 'include': 'include-cycle.json' }
H A Dinclude-self-cycle.json1 { 'include': 'include-self-cycle.json' }
H A Dinclude-cycle.json1 { 'include': 'include-cycle-b.json' }
H A Dinclude-cycle-b.json1 { 'include': 'include-cycle-c.json' }
/qemu/hw/riscv/
H A Driscv-iommu-hpm.c27 /* For now we assume IOMMU HPM frequency to be 1GHz so 1-cycle is of 1-ns. */
35 const uint64_t cycle = riscv_iommu_reg_get64( in riscv_iommu_hpmcycle_read() local
42 trace_riscv_iommu_hpm_read(cycle, inhibit, ctr_prev, ctr_val); in riscv_iommu_hpmcycle_read()
51 (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF); in riscv_iommu_hpmcycle_read()
55 (cycle & RISCV_IOMMU_IOHPMCYCLES_OVF); in riscv_iommu_hpmcycle_read()
71 * Generate interrupt only if OF bit is clear. +1 to offset the cycle in hpm_incr_ctr()
174 /* Timer callback for cycle counter overflow. */
221 * We are using INT64_MAX here instead to UINT64_MAX because cycle counter in hpm_setup_timer()
240 /* Updates the internal cycle counter state when iocntinh:CY is changed. */
255 * Cycle counter is enabled. Just start the timer again and update in riscv_iommu_process_iocntinh_cy()
[all …]
H A Dtrace-events22 riscv_iommu_hpm_read(uint64_t cycle, uint32_t inhibit, uint64_t ctr_prev, uint64_t ctr_val) "cycle …
H A Driscv-iommu.h85 /* HPM cycle counter */
87 uint64_t hpmcycle_val; /* Current value of cycle register */
/qemu/migration/
H A Dmigration-stats.h89 * Amount of transferred data at the start of current cycle.
93 * Maximum amount of data we can send in a cycle.
111 * Returns the maximum number of bytes that can be transferred in a cycle.
118 * This is called when we know we start a new transfer cycle.
125 * Sets the maximum amount of bytes that can be transferred in one cycle.
/qemu/include/hw/misc/
H A Dnpcm7xx_pwm.h35 * value of 100,000 the duty cycle for that PWM is 10%.
53 * @duty: The duty cycle of this PWM channel. One unit represents
80 * @duty_gpio_out: The duty cycle of each PWM channels as a output GPIO.
/qemu/hw/char/
H A Dparallel.c171 /* Controls not correct for EPP address cycle, so do nothing */ in parallel_ioport_write_hw()
186 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_write_hw()
213 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw2()
238 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_write_hw4()
326 /* Controls not correct for EPP addr cycle, so do nothing */ in parallel_ioport_read_hw()
342 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_read_hw()
371 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_read_hw2()
399 /* Controls not correct for EPP data cycle, so do nothing */ in parallel_ioport_eppdata_read_hw4()
/qemu/hw/sh4/
H A Dsh7750_regs.h677 #define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle */
680 #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */
682 #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */
684 #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */
686 #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */
688 #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */
690 #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */
692 #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */
740 #define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */
750 #define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */
[all …]
/qemu/hw/nvram/
H A Deeprom93xx.c166 /* Start chip select cycle. */ in eeprom93xx_write()
167 logout("Cycle start, waiting for 1st start bit (0)\n"); in eeprom93xx_write()
172 /* End chip select cycle. This triggers write / erase. */ in eeprom93xx_write()
/qemu/target/ppc/
H A Dpower8-pmu.c210 * that 1 nanosec equals 1 cycle. in pmu_update_cycles()
221 * Helper function to retrieve the cycle overflow timer of the
297 /* Update cycle overflow timers with the current MMCR0 state */ in helper_store_mmcr0()
/qemu/tests/qtest/libqos/
H A Dlibqos.c175 /* Write an indicative pattern that varies and is unique per-cycle */ in generate_pattern()
184 /* force uniqueness by writing an id per-cycle */ in generate_pattern()
/qemu/tests/tcg/riscv64/
H A Dissue1060.S14 csrw cycle, x0
/qemu/include/system/
H A Dcpu-timers.h29 * cpu_get_ticks() uses units of the host CPU cycle counter.
/qemu/tests/tcg/plugins/
H A Dreset.c4 * Test the reset/uninstall cycle of a plugin.
/qemu/docs/system/devices/
H A Dvirtio-snd.rst25 …eam, an optional second will always be a capture stream. Adding more will cycle stream directions …
/qemu/docs/devel/
H A Dqom.rst303 can be found at :ref:`device-life-cycle`.
433 .. _device-life-cycle:
435 Device Life-cycle
/qemu/hw/audio/
H A Dasc.c258 * interrupts to be generated for each FIFO cycle (without these interrupts in generate_fifo()
263 /* FIFO has completed first empty cycle */ in generate_fifo()
266 /* FIFO has completed entire cycle with no data */ in generate_fifo()
352 * No new FIFO data within half a cycle time (~23ms) so fill the in asc_out_cb()

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