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/linux-5.10/Documentation/arm/stm32/
Dstm32f429-overview.rst6 ------------
8 The STM32F429 is a Cortex-M4 MCU aimed at various applications.
11 - ARM Cortex-M4 up to 180MHz with FPU
12 - 2MB internal Flash Memory
13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
14 - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
15 - LCD controller & Camera interface
16 - Cryptographic processor
19 ---------
23 …www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
/linux-5.10/arch/arm/boot/dts/
Dvf610m4-colibri.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Device tree for Colibri VF61 Cortex-M4 support
8 /dts-v1/;
12 model = "VF610 Cortex-M4";
17 stdout-path = "serial2:115200";
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart2>;
53 vf610-colibri {
Dvf610m4-cosmic.dts2 * Device tree for Cosmic+ VF6xx Cortex-M4 support
8 * This file is dual-licensed: you can use it either under the terms
47 /dts-v1/;
51 model = "VF610 Cortex-M4";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_uart3>;
82 vf610-cosmic {
Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
Dlpc4357.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
Dvf610m4.dtsi2 * Device tree for VF6xx Cortex-M4 support
6 * This file is dual-licensed: you can use it either under the terms
45 #include "armv7-m.dtsi"
49 #address-cells = <1>;
50 #size-cells = <1>;
56 interrupt-parent = <&nvic>;
Dimx6sx-udoo-neo.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 stdout-path = "serial0:115200n8";
16 compatible = "gpio-leds";
19 label = "udoo-neo:red:mmc";
21 default-state = "off";
22 linux,default-trigger = "mmc0";
26 label = "udoo-neo:orange:user";
28 default-state = "keep";
32 reg_sdio_pwr: regulator-sdio-pwr {
33 compatible = "regulator-fixed";
[all …]
Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
/linux-5.10/arch/arm/mm/
Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: STMicroelectronics STM32 ML-AHB interconnect bindings
10 - Fabien Dessenne <fabien.dessenne@st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
[all …]
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
[all …]
/linux-5.10/arch/arm/mach-imx/
Dmach-imx7d-cm4.c1 // SPDX-License-Identifier: GPL-2.0
11 "fsl,imx7d-cm4",
15 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
/linux-5.10/drivers/firmware/imx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 The System Controller Firmware (SCFW) is a low-level system function
18 which runs on a dedicated Cortex-M core to provide power, clock, and
23 SCU firmware running on M4.
/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dimx-rproc.txt1 NXP iMX6SX/iMX7D Co-Processor Bindings
2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be one of:
9 "fsl,imx7d-cm4"
10 "fsl,imx6sx-cm4"
11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
12 - syscon Phandle to syscon block which provide access to
16 - memory-region list of phandels to the reserved memory regions.
17 (See: ../reserved-memory/reserved-memory.txt)
[all …]
Dmtk,scp.txt2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be "mediatek,mt8183-scp"
9 - reg Should contain the address ranges for the two memory
11 - reg-names Contains the corresponding names for the two memory
13 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
14 - clock-names Contains the corresponding name for the clock. This
18 --------
22 for the rpmsg devices - but must contain the following property:
24 - mtk,rpmsg-name Contains the name for the rpmsg device. Used to match
[all …]
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
/linux-5.10/drivers/remoteproc/
Dimx_rproc.c1 // SPDX-License-Identifier: GPL-2.0-only
49 * struct imx_rproc_mem - slim internal memory structure
61 /* M4 own area. Can be mapped at probe */
66 u32 da; /* device address (From Cortex M4 view)*/
92 /* OCRAM_S (M4 Boot code) - alias */
96 /* OCRAM (Code) - alias */
98 /* OCRAM_EPDC (Code) - alias */
100 /* OCRAM_PXP (Code) - alias */
104 /* DDR (Code) - alias, first part of DDR (Data) */
121 /* TCML (M4 Boot Code) - alias */
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
30 Say y here to support iMX's remote processors (Cortex M4
41 This can be either built-in or a loadable module.
67 use-cases to run on your platform (multimedia codecs are
92 Required for Suspend-to-RAM on AM33xx and AM43xx SoCs. Also needed
98 tristate "DA8xx/OMAP-L13x remoteproc support"
102 Say y here to support DA8xx/OMAP-L13x remote processors via the
106 use-cases to run on your platform (multimedia codecs are
113 "rproc-dsp-fw".
156 tristate "Qualcomm Hexagon V5 self-authenticating modem subsystem support"
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/linux-5.10/arch/arm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
129 The ARM series is a line of low-power-consumption RISC chip designs
131 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
132 manufactured, but legacy ARM-based PC hardware remains popular in
242 Patch phys-to-virt and virt-to-phys translation functions at
246 This can only be used with non-XIP MMU kernels where the base
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 bool "EBSA-110"
[all …]
/linux-5.10/drivers/irqchip/
Dirq-vf610-mscm-ir.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2015 Toradex AG
9 * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
10 * Cortex-M4). The router will be configured transparently on a IRQ
14 * CPU 0, CPU 1 or both. The routing is useful for dual-core
18 * o It is required to setup the interrupt router even on single-core
28 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i)); in vf610_mscm_ir_save()
63 writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i)); in vf610_mscm_ir_restore()
88 irq_hw_number_t hwirq = data->hwirq; in vf610_mscm_ir_enable()
[all …]
Dirq-nvic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
9 * ARMv7-M CPUs (Cortex-M3/M4)
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
85 return -ENOMEM; in nvic_of_init()
97 return -ENOMEM; in nvic_of_init()
113 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
114 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
115 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
116 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in nvic_of_init()
[all …]
/linux-5.10/Documentation/devicetree/bindings/mfd/
Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
12 - Guenter Roeck <groeck@chromium.org>
23 - description:
25 const: google,cros-ec-i2c
26 - description:
[all …]
/linux-5.10/drivers/gpio/
Dgpio-lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0
59 u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
66 writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
72 writel_relaxed(BIT(pin), ic->base + reg); in lpc18xx_gpio_pin_ic_set()
77 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_mask()
80 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
83 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
87 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
90 raw_spin_unlock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
97 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_unmask()
[all …]

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