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/qemu/hw/net/
H A De1000e_core.c2 * Core code for QEMU e1000e emulation
66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
72 static void e1000e_reset(E1000ECore *core, bool sw);
75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp) in e1000e_process_ts_option() argument
83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length) in e1000e_process_snap_option() argument
91 e1000e_raise_legacy_irq(E1000ECore *core) in e1000e_raise_legacy_irq() argument
94 e1000x_inc_reg_if_not_full(core->mac, IAC); in e1000e_raise_legacy_irq()
95 pci_set_irq(core->owner, 1); in e1000e_raise_legacy_irq()
99 e1000e_lower_legacy_irq(E1000ECore *core) in e1000e_lower_legacy_irq() argument
[all …]
H A Digb_core.c2 * Core code for QEMU igb emulation
66 IGBCore *core; member
94 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
97 static void igb_raise_interrupts(IGBCore *core, size_t index, uint32_t causes);
98 static void igb_reset(IGBCore *core, bool sw);
101 igb_raise_legacy_irq(IGBCore *core) in igb_raise_legacy_irq() argument
104 e1000x_inc_reg_if_not_full(core->mac, IAC); in igb_raise_legacy_irq()
105 pci_set_irq(core->owner, 1); in igb_raise_legacy_irq()
109 igb_lower_legacy_irq(IGBCore *core) in igb_lower_legacy_irq() argument
112 pci_set_irq(core->owner, 0); in igb_lower_legacy_irq()
[all …]
H A De1000e.c82 E1000ECore core; member
104 return e1000e_core_read(&s->core, addr, size); in e1000e_mmio_read()
112 e1000e_core_write(&s->core, addr, val, size); in e1000e_mmio_write()
150 val = e1000e_core_read(&s->core, idx, sizeof(val)); in e1000e_io_read()
176 e1000e_core_write(&s->core, idx, val, sizeof(val)); in e1000e_io_write()
209 return e1000e_can_receive(&s->core); in e1000e_nc_can_receive()
216 return e1000e_receive_iov(&s->core, iov, iovcnt); in e1000e_nc_receive_iov()
223 return e1000e_receive(&s->core, buf, size); in e1000e_nc_receive()
230 e1000e_core_set_link_status(&s->core); in e1000e_set_link_status()
267 s->core.owner = &s->parent_obj; in e1000e_core_realize()
[all …]
H A Digb_core.h2 * Core code for QEMU igb emulation
63 IGBCore *core; member
105 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size);
108 igb_core_read(IGBCore *core, hwaddr addr, unsigned size);
117 igb_core_reset(IGBCore *core);
120 igb_core_pre_save(IGBCore *core);
123 igb_core_post_load(IGBCore *core);
126 igb_core_set_link_status(IGBCore *core);
129 igb_core_pci_uninit(IGBCore *core);
132 igb_core_vf_reset(IGBCore *core, uint16_t vfn);
[all …]
H A De1000e_core.h2 * Core code for QEMU e1000e emulation
58 E1000ECore *core; member
116 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size);
119 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size);
128 e1000e_core_reset(E1000ECore *core);
131 e1000e_core_pre_save(E1000ECore *core);
134 e1000e_core_post_load(E1000ECore *core);
137 e1000e_core_set_link_status(E1000ECore *core);
140 e1000e_core_pci_uninit(E1000ECore *core);
143 e1000e_can_receive(E1000ECore *core);
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H A Digb.c80 IGBCore core; member
111 igb_start_recv(&s->core); in igb_write_config()
119 return igb_core_read(&s->core, addr, size); in igb_mmio_read()
126 igb_core_write(&s->core, addr, val, size); in igb_mmio_write()
132 igb_core_vf_reset(&s->core, vfn); in igb_vf_reset()
170 val = igb_core_read(&s->core, idx, sizeof(val)); in igb_io_read()
195 igb_core_write(&s->core, idx, val, sizeof(val)); in igb_io_write()
228 return igb_can_receive(&s->core); in igb_nc_can_receive()
235 return igb_receive_iov(&s->core, iov, iovcnt); in igb_nc_receive_iov()
242 return igb_receive(&s->core, buf, size); in igb_nc_receive()
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/qemu/audio/
H A Dcoreaudio.m245 static int coreaudio_buf_lock (coreaudioVoiceOut *core, const char *fn_name)
249 err = pthread_mutex_lock (&core->buf_mutex);
258 static int coreaudio_buf_unlock (coreaudioVoiceOut *core, const char *fn_name)
262 err = pthread_mutex_unlock (&core->buf_mutex);
274 coreaudioVoiceOut *core = (coreaudioVoiceOut *) hw; \
277 if (coreaudio_buf_lock(core, "coreaudio_" #name)) { \
283 coreaudio_buf_unlock(core, "coreaudio_" #name); \
312 coreaudioVoiceOut *core = (coreaudioVoiceOut *) hwptr;
315 if (coreaudio_buf_lock (core, "audioDeviceIOProc")) {
320 if (inDevice != core->outputDeviceID) {
[all …]
/qemu/target/xtensa/
H A Dcores.list1 core-dc232b.c
2 core-dc233c.c
3 core-de212.c
4 core-de233_fpu.c
5 core-dsp3400.c
6 core-fsf.c
7 core-lx106.c
8 core-sample_controller.c
9 core-test_kc705_be.c
10 core-test_mmuhifi_c3.c
H A Dimport_core.sh7 TARGET="$BASE"/core-$NAME
10 Usage: $0 overlay-archive-to-import core-name [frequency-in-KHz]
13 core-name: QEMU name of the imported core. Must be valid
15 frequency-in-KHz: core frequency (40MHz if not specified).
23 xtensa/config/core-isa.h \
24 xtensa/config/core-matmap.h
47 #include "core-$NAME/core-isa.h"
48 #include "core-$NAME/core-matmap.h"
52 #include "core-$NAME/xtensa-modules.c.inc"
58 #include "core-$NAME/gdb-config.c.inc"
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/qemu/hw/cpu/
H A Dcore.c2 * CPU core abstract device
13 #include "hw/cpu/core.h"
20 CPUCore *core = CPU_CORE(obj); in core_prop_get_core_id() local
21 int64_t value = core->core_id; in core_prop_get_core_id()
29 CPUCore *core = CPU_CORE(obj); in core_prop_set_core_id() local
37 error_setg(errp, "Invalid core id %"PRId64, value); in core_prop_set_core_id()
41 core->core_id = value; in core_prop_set_core_id()
47 CPUCore *core = CPU_CORE(obj); in core_prop_get_nr_threads() local
48 int64_t value = core->nr_threads; in core_prop_get_nr_threads()
56 CPUCore *core = CPU_CORE(obj); in core_prop_set_nr_threads() local
[all …]
/qemu/docs/system/s390x/
H A Dcpu-topology.rst17 Each bit set in the bitmap correspond to a core-id of a vCPU with matching
77 based on the core-id starting with core-0 at position 0 of socket-0,
87 -device gen16b-s390x-cpu,drawer-id=1,book-id=1,socket-id=2,core-id=1
93 -device gen16b-s390x-cpu,core-id=1,dedicated=true
98 adding the CPUs to the topology based on the core-id.
119 (qemu) device_add gen16b-s390x-cpu,core-id=9
121 The placement of the CPU is derived from the core-id as described above.
127 (qemu) device_add gen16b-s390x-cpu,drawer-id=1,book-id=1,socket-id=2,core-id=1
140 -device host-s390x-cpu,core-id=14 \
146 (qemu) device_add gen16b-s390x-cpu,core-id=9
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/qemu/hw/intc/
H A Dloongarch_ipi.c106 IPICore *core; in loongarch_ipi_reset_hold() local
113 core = lics->cpu + i; in loongarch_ipi_reset_hold()
115 if (!core->cpu) { in loongarch_ipi_reset_hold()
119 core->status = 0; in loongarch_ipi_reset_hold()
120 core->en = 0; in loongarch_ipi_reset_hold()
121 core->set = 0; in loongarch_ipi_reset_hold()
122 core->clear = 0; in loongarch_ipi_reset_hold()
123 memset(core->buf, 0, sizeof(core->buf)); in loongarch_ipi_reset_hold()
136 IPICore *core; in loongarch_ipi_cpu_plug() local
145 core = loongarch_ipi_get_cpu(lics, dev); in loongarch_ipi_cpu_plug()
[all …]
H A Dloongson_liointc.c52 uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */
64 uint32_t irq, core, ip; in update_irq() local
74 for (core = 0; core < NUM_CORES; core++) { in update_irq()
75 p->per_core_isr[core] = 0; in update_irq()
84 for (core = 0; core < NUM_CORES; core++) { in update_irq()
85 if ((p->mapper[irq] & (1 << core))) { in update_irq()
86 p->per_core_isr[core] |= (1 << irq); in update_irq()
98 for (core = 0; core < NUM_CORES; core++) { in update_irq()
100 int parent = PARENT_COREx_IPy(core, ip); in update_irq()
102 (!!p->per_core_isr[core] && !!per_ip_isr[ip])) { in update_irq()
[all …]
H A Dloongarch_extioi_common.c36 ExtIOICore *core; in loongarch_extioi_cpu_plug() local
45 core = loongarch_extioi_get_cpu(s, dev); in loongarch_extioi_cpu_plug()
46 if (!core) { in loongarch_extioi_cpu_plug()
50 core->cpu = CPU(dev); in loongarch_extioi_cpu_plug()
51 index = core - s->cpu; in loongarch_extioi_cpu_plug()
68 ExtIOICore *core; in loongarch_extioi_cpu_unplug() local
76 core = loongarch_extioi_get_cpu(s, dev); in loongarch_extioi_cpu_unplug()
77 if (!core) { in loongarch_extioi_cpu_unplug()
81 core->cpu = NULL; in loongarch_extioi_cpu_unplug()
115 ExtIOICore *core; in loongarch_extioi_common_reset_hold() local
[all …]
H A Dloongarch_ipi_kvm.c24 IPICore *core; in kvm_ipi_access_regs() local
33 core = &ipi->cpu[cpu]; in kvm_ipi_access_regs()
35 kvm_ipi_access_reg(fd, attr, &core->status, write); in kvm_ipi_access_regs()
38 kvm_ipi_access_reg(fd, attr, &core->en, write); in kvm_ipi_access_regs()
41 kvm_ipi_access_reg(fd, attr, &core->set, write); in kvm_ipi_access_regs()
44 kvm_ipi_access_reg(fd, attr, &core->clear, write); in kvm_ipi_access_regs()
47 kvm_ipi_access_reg(fd, attr, &core->buf[0], write); in kvm_ipi_access_regs()
50 kvm_ipi_access_reg(fd, attr, &core->buf[2], write); in kvm_ipi_access_regs()
53 kvm_ipi_access_reg(fd, attr, &core->buf[4], write); in kvm_ipi_access_regs()
56 kvm_ipi_access_reg(fd, attr, &core->buf[6], write); in kvm_ipi_access_regs()
H A Dbcm2836_control.c63 static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq, in deliver_local() argument
68 s->fiqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
71 s->irqsrc[core] |= (uint32_t)1 << irq; in deliver_local()
113 /* handle local timer interrupts for this core */ in bcm2836_control_update()
124 /* handle mailboxes for this core */ in bcm2836_control_update()
140 static void bcm2836_control_set_local_irq(void *opaque, int core, int local_irq, in bcm2836_control_set_local_irq() argument
145 assert(core >= 0 && core < BCM2836_NCORES); in bcm2836_control_set_local_irq()
148 s->timerirqs[core] = deposit32(s->timerirqs[core], local_irq, 1, !!level); in bcm2836_control_set_local_irq()
158 static void bcm2836_control_set_local_irq0(void *opaque, int core, int level) in bcm2836_control_set_local_irq0() argument
160 bcm2836_control_set_local_irq(opaque, core, IRQ_CNTPSIRQ, level); in bcm2836_control_set_local_irq0()
[all …]
/qemu/include/hw/ppc/
H A Dpnv_xscom.h41 * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
57 #define PNV_XSCOM_EX_BASE(core) \ argument
58 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
91 #define PNV9_XSCOM_EC_BASE(core) \ argument
92 ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
95 #define PNV9_XSCOM_EQ_BASE(core) \ argument
96 ((uint64_t)(((core) & 0x1C) + 0x40) << 22)
142 #define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2)) argument
154 #define PNV10_XSCOM_QME_BASE(core) \ argument
155 ((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core)))
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H A Dpnv_core.h2 * QEMU PowerPC PowerNV CPU Core model
23 #include "hw/cpu/core.h"
28 /* Per-core ChipTOD / TimeBase state */
31 * POWER10 DD2.0 - big core TFMR drives the state machine on the even
32 * small core. Skiboot has a workaround that targets the even small core
37 int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
38 int tod_sent_to_tb; /* chiptod sent TOD to the core TB */
49 #define TYPE_PNV_CORE "powernv-cpu-core"
/qemu/tests/functional/
H A Dtest_s390x_topology.py66 core = cpu['props']['core-id']
72 if core == c:
156 {'core-id': 0, 'socket-id': 2, 'entitlement': 'low'})
169 self.vm.add_args('-device', 'max-s390x-cpu,core-id=10')
172 'core-id=1,socket-id=0,book-id=1,drawer-id=1,entitlement=low')
175 'core-id=2,socket-id=0,book-id=1,drawer-id=1,entitlement=medium')
178 'core-id=3,socket-id=1,book-id=1,drawer-id=1,entitlement=high')
181 'core-id=4,socket-id=1,book-id=1,drawer-id=1')
184 'core-id=5,socket-id=2,book-id=1,drawer-id=1,dedicated=true')
269 {'core-id': 0, 'entitlement': 'low'})
[all …]
/qemu/tests/qtest/
H A Dnuma-test.c132 "-numa cpu,node-id=0,socket-id=1,core-id=0 " in pc_numa_cpu()
133 "-numa cpu,node-id=0,socket-id=1,core-id=1,thread-id=0 " in pc_numa_cpu()
134 "-numa cpu,node-id=1,socket-id=1,core-id=1,thread-id=1"); in pc_numa_cpu()
141 int64_t socket, core, thread, node; in pc_numa_cpu() local
151 g_assert(qdict_haskey(props, "core-id")); in pc_numa_cpu()
152 core = qdict_get_int(props, "core-id"); in pc_numa_cpu()
158 } else if (socket == 1 && core == 0) { in pc_numa_cpu()
160 } else if (socket == 1 && core == 1 && thread == 0) { in pc_numa_cpu()
162 } else if (socket == 1 && core == 1 && thread == 1) { in pc_numa_cpu()
184 "-numa cpu,node-id=0,core-id=0 " in spapr_numa_cpu()
[all …]
H A Dpnv-xscom-test.c48 #define PNV_XSCOM_EX_BASE(core) \ argument
49 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
50 #define PNV_XSCOM_P9_EC_BASE(core) \ argument
51 ((uint64_t)(((core) & 0x1F) + 0x20) << 24)
52 #define PNV_XSCOM_P10_EC_BASE(core) \ argument
53 ((uint64_t)((((core) & ~0x3) + 0x20) << 24) + 0x20000 + \
54 (0x1000 << (3 - (core & 0x3))))
119 add_test("core", test_core); in main()
/qemu/hw/arm/
H A Dbcm2836.c31 object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, in bcm283x_base_init()
95 if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) { in bcm2835_realize()
101 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ)); in bcm2835_realize()
103 qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ)); in bcm2835_realize()
132 object_property_set_int(OBJECT(&s_base->cpu[n].core), "mp-affinity", in bcm2836_realize()
136 object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-cbar", in bcm2836_realize()
140 object_property_set_bool(OBJECT(&s_base->cpu[n].core), in bcm2836_realize()
144 if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) { in bcm2836_realize()
150 qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_IRQ)); in bcm2836_realize()
152 qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_FIQ)); in bcm2836_realize()
[all …]
/qemu/rust/qemu-api/src/
H A Dvmstate.rs27 use core::{marker::PhantomData, mem, ptr::NonNull};
44 /// # use core::marker::PhantomData;
63 … const fn phantom__<T>(_: &T) -> ::core::marker::PhantomData<T> { ::core::marker::PhantomData }
66 break ::core::marker::PhantomData;
100 $crate::vmstate::VMStateFieldType::null => ::core::ptr::null(),
102 ::core::ptr::addr_of!($crate::bindings::vmstate_info_bool)
105 ::core::ptr::addr_of!($crate::bindings::vmstate_info_int8)
108 ::core::ptr::addr_of!($crate::bindings::vmstate_info_int16)
111 ::core::ptr::addr_of!($crate::bindings::vmstate_info_int32)
114 ::core::ptr::addr_of!($crate::bindings::vmstate_info_int64)
[all …]
/qemu/docs/devel/
H A Ds390-cpu-topology.rst16 -device z14-s390x-cpu,core-id=19,entitlement=high \
17 -device z14-s390x-cpu,core-id=11,entitlement=low \
18 -device z14-s390x-cpu,core-id=12,entitlement=high \
36 "core-id": 0,
51 "core-id": 19,
66 "core-id": 11,
81 "core-id": 12,
106 "core-id": 11,
116 The core-id parameter is the only mandatory parameter and every
/qemu/docs/system/
H A Dcpu-hotplug.rst37 "core-id": 1,
46 "core-id": 0,
61 can see that ``IvyBridge-IBRS-x86_64-cpu`` is present in socket 0 core 0,
62 while hot-plugging a CPU into socket 0 core 1 requires passing the listed
65 (QEMU) device_add id=cpu-2 driver=IvyBridge-IBRS-x86_64-cpu socket-id=0 core-id=1 thread-id=0
69 "core-id": 1,
94 "core-id": 0,
105 "core-id": 1,

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