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/linux-6.8/lib/
Dsort.c1 // SPDX-License-Identifier: GPL-2.0
3 * A fast, small, non-recursive O(n log n) sort for the Linux kernel
6 * and 1.5*n*log2(n) + O(n) in the (very contrived) worst case.
8 * Glibc qsort() manages n*log2(n) - 1.26*n for random inputs (1.63*n
9 * better) at the expense of stack usage and much larger code to avoid
20 * is_aligned - is this pointer & size okay for word-wide copying?
25 * Returns true if elements can be copied using word loads and stores.
26 * The size must be a multiple of the alignment, and the base address must
41 return (lsbits & (align - 1)) == 0; in is_aligned()
45 * swap_words_32 - swap two elements in 32-bit chunks
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/linux-6.8/arch/xtensa/kernel/
Ds32c1i_selftest.c4 * This file is subject to the terms and conditions of the GNU General Public
21 * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
45 if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */ in do_probed_exception()
46 regs->pc += 3; /* skip the s32c1i instruction */ in do_probed_exception()
47 rcw_exc = regs->exccause; in do_probed_exception()
80 panic("S32C1I compare error"); in check_s32c1i()
121 pr_warn("Processor configuration lacks atomic compare-and-swap support!\n"); in check_s32c1i()
/linux-6.8/arch/m68k/ifpsp060/src/
Dilsp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 and any warranty against infringement with regard to the SOFTWARE label
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24 so long as this entire notice is retained without alteration in any modified and/or
25 redistributed versions, and that such modified versions are clearly identified as such.
31 # and contains the entry points into the package. The user, in
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Disp.S3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 and any warranty against infringement with regard to the SOFTWARE label
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24 so long as this entire notice is retained without alteration in any modified and/or
25 redistributed versions, and that such modified versions are clearly identified as such.
31 # and contains the entry points into the package. The user, in
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/linux-6.8/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s5 * This program is free software; you can redistribute it and/or modify
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
43 swap:
99 // $r0 is always set to 0 in our code - this allows some space savings.
109 // set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host
119 // enable fifo access and context switching
138 and $r2 $r1 0x8
146 // 128-byte context.
158 // unload the current channel - save the context
161 // and clear bit 30, then write back
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/linux-6.8/arch/s390/tools/
Dgen_facilities.c1 // SPDX-License-Identifier: GPL-2.0
26 * -march=<machine>.
33 21, /* extended-immediate facility */
36 32, /* compare and swap and store */
37 33, /* compare and swap and store 2 */
41 45, /* fast-BCR, etc. */
44 49, /* misc-instruction-extensions */
48 53, /* load-and-zero-rightmost-byte, etc. */
52 58, /* miscellaneous-instruction-extension 2 */
55 61, /* miscellaneous-instruction-extension 3 */
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/linux-6.8/drivers/misc/genwqe/
Dcard_ddcb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
23 * struct ddcb - Device Driver Control Block DDCB
25 * @shi: Software hardware interlock. Hsi and shi are used to interlock
26 * software and hardware activities. We are using a compare and
27 * swap operation to ensure that there are no races when
120 * Accessing HSI/SHI is done 32-bit wide
121 * Normally 16-bit access would work too, but on some platforms the
122 * 16 compare and swap operation is not supported. Therefore
123 * switching to 32-bit such that those platforms will work too.
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/linux-6.8/arch/xtensa/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
21 #define SYS_XTENSA_ATOMIC_EXG_ADD 2 /* exchange memory and add */
23 #define SYS_XTENSA_ATOMIC_CMP_SWP 4 /* compare and swap */
/linux-6.8/arch/m68k/lib/
Dudivsi3.S1 /* libgcc1 routines for 68000 w/o floating-point hardware.
6 GNU CC is free software; you can redistribute it and/or modify it
13 compiled version of this file with other programs, and to distribute
16 respects; for example, they cover modification of the file, and
33 D. V. Henkel-Wallace (gumby@cygnus.com) Fete Bastille, 1992
90 movel d2, sp@-
98 swap d2 define
101 swap d0 define
120 swap d2 define
122 swap d2 /* align high part with low part */ define
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/linux-6.8/arch/sh/include/uapi/asm/
Dcpu-features.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
19 #define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
24 #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
26 #define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */
/linux-6.8/include/uapi/linux/
Drds.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
3 * Copyright (c) 2008, 2018 Oracle and/or its affiliates. All rights reserved.
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
71 /* don't use RDS_TRANS_IWARP - it is deprecated */
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/linux-6.8/fs/bcachefs/
Dbkey_sort.c1 // SPDX-License-Identifier: GPL-2.0
15 return !iter->used; in sort_iter_end()
24 i + 1 < iter->used && in sort_iter_sift()
25 cmp(iter->b, iter->data[i].k, iter->data[i + 1].k) > 0; in sort_iter_sift()
27 swap(iter->data[i], iter->data[i + 1]); in sort_iter_sift()
32 unsigned i = iter->used; in sort_iter_sort()
34 while (i--) in sort_iter_sort()
40 return !sort_iter_end(iter) ? iter->data->k : NULL; in sort_iter_peek()
45 struct sort_iter_set *i = iter->data; in sort_iter_advance()
47 BUG_ON(!iter->used); in sort_iter_advance()
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/linux-6.8/arch/sparc/include/asm/
Dbackoff.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * completion of the compare-and-swap instruction. Heavily
14 * When an atomic operation fails and needs to be retried, we spin a
20 * current cpu strand to block, and therefore make the core fully
24 * On all cpus prior to SPARC-T4 we do three dummy reads of the
26 * between 40 and 50 cpu cycles.
28 * For SPARC-T4 and later we have a special "pause" instruction
31 * unless a disrupting trap happens first. SPARC-T4 specifically
34 * chip shifts the %asr27 value down by 3 bits, and writes the result
/linux-6.8/arch/x86/include/asm/
Dmc146818rtc.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 * special properties. It is owned by a CPU and stores the index register
24 * and performs the access and then restores the index register. If it does
28 * a non-SMP machine just to mark that the lock is owned.
30 * This only works with compare-and-swap. There is no other way to
31 * atomically claim the lock and set the owner.
/linux-6.8/include/uapi/rdma/
Dvmw_pvrdma-abi.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
3 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
5 * This program is free software; you can redistribute it and/or
8 * 2-Clause License. This program is distributed in the hope that it
12 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
18 * The BSD 2-Clause License
20 * Redistribution and use in source and binary forms, with or
24 * - Redistributions of source code must retain the above
25 * copyright notice, this list of conditions and the following
28 * - Redistributions in binary form must reproduce the above
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/linux-6.8/net/rds/
Drdma.c2 * Copyright (c) 2007, 2020 Oracle and/or its affiliates.
10 * Redistribution and use in source and binary forms, with or
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 #include <linux/dma-mapping.h> /* for DMA_*_DEVICE */
42 * - build with sparse
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/linux-6.8/arch/powerpc/kvm/
Dbook3s_xics.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * We use a two-level tree to store interrupt source information.
19 #define KVMPPC_XICS_SRC_MASK (KVMPPC_XICS_IRQ_PER_ICS - 1)
23 * 0 is "no interrupt", and 2 is used for IPIs.
44 u8 lsi; /* level-sensitive interrupt */
50 /* Atomic ICP state, updated with a single compare & swap */
122 if (vcpu->arch.icp && nr == vcpu->arch.icp->server_num) in kvmppc_xics_find_server()
123 return vcpu->arch.icp; in kvmppc_xics_find_server()
139 ics = xics->ics[icsid]; in kvmppc_xics_find_ics()
/linux-6.8/arch/s390/include/asm/
Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * to any CPU and may be used for translation by that CPU except to
12 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
13 * table entry, or (3) make a change by means of a COMPARE AND SWAP
14 * AND PURGE instruction that purges the TLB."
38 #include <asm-generic/tlb.h>
58 __tlb_flush_mm_lazy(tlb->mm); in tlb_flush()
62 * pte_free_tlb frees a pte table and clears the CRSTE for the
69 tlb->mm->context.flush_mm = 1; in pte_free_tlb()
70 tlb->freed_tables = 1; in pte_free_tlb()
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/linux-6.8/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
85 #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
113 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
114 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
115 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
116 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
117 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
134 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
135 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
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/linux-6.8/drivers/infiniband/hw/vmw_pvrdma/
Dpvrdma_dev_api.h2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
4 * This program is free software; you can redistribute it and/or
7 * 2-Clause License. This program is distributed in the hope that it
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
17 * The BSD 2-Clause License
19 * Redistribution and use in source and binary forms, with or
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
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/linux-6.8/fs/btrfs/
Dctree.h1 /* SPDX-License-Identifier: GPL-2.0 */
42 * will still trigger readahead for other nodes and leaves that follow
53 * level 0 is always the leaf, and nodes[1...BTRFS_MAX_LEVEL] will point
70 * and to force calls to keep space in the nodes
80 * existing item and ins_len contains only the data size and not item
93 * btrfs_record_root_in_trans is a multi-step process, and it can race
94 * with the balancing code. But the race is very small, and only the
102 * Only subvolume trees and their reloc trees have this bit set.
107 * - How balance works
108 * For shareable roots, we need to use reloc tree and do path
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/linux-6.8/Documentation/
Datomic_t.txt2 On atomic types (atomic_t atomic64_t and atomic_long_t).
5 RMW operations between CPUs (atomic operations on MMIO are not supported and
9 ---
11 The 'full' API consists of (atomic64_ and atomic_long_ prefixes omitted for
14 Non-RMW ops:
31 atomic_{and,or,xor,andnot}()
32 atomic_fetch_{and,or,xor,andnot}{,_relaxed,_acquire,_release}()
35 Swap:
60 -----
62 While atomic_t, atomic_long_t and atomic64_t use int, long and s64
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/linux-6.8/lib/zstd/compress/
Dzstd_fast.c5 * This source code is licensed under both the BSD-style license (found in the
6 * LICENSE file in the root directory of this source tree) and the GPLv2 (found
8 * You may select, at your option, one of the above-listed licenses.
19 const ZSTD_compressionParameters* const cParams = &ms->cParams; in ZSTD_fillHashTable()
20 U32* const hashTable = ms->hashTable; in ZSTD_fillHashTable()
21 U32 const hBits = cParams->hashLog; in ZSTD_fillHashTable()
22 U32 const mls = cParams->minMatch; in ZSTD_fillHashTable()
23 const BYTE* const base = ms->window.base; in ZSTD_fillHashTable()
24 const BYTE* ip = base + ms->nextToUpdate; in ZSTD_fillHashTable()
25 const BYTE* const iend = ((const BYTE*)end) - HASH_READ_SIZE; in ZSTD_fillHashTable()
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/linux-6.8/drivers/s390/cio/
Dqdio_thinint.c1 // SPDX-License-Identifier: GPL-2.0
35 u32 ind; /* u32 because of compare-and-swap performance */
36 atomic_t count; /* use count, 0 or 1 for non-shared indicators */
67 atomic_dec(&ind->count); in put_indicator()
72 return irq_ptr->dsci == &q_indicators[TIQDIO_SHARED_IND].ind; in references_shared_dsci()
81 if (*irq_ptr->dsci) in test_nonshared_ind()
95 * tiqdio_thinint_handler - thin interrupt handler for qdio
97 * @tpi_info: interrupt information (e.g. floating vs directed -- unused)
118 if (!*irq->dsci) in tiqdio_thinint_handler()
121 xchg(irq->dsci, 0); in tiqdio_thinint_handler()
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/linux-6.8/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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