| /linux/drivers/net/wireless/broadcom/brcm80211/brcmutil/ |
| H A D | d11.c | 41 static void brcmu_d11n_encchspec(struct brcmu_chan *ch) in brcmu_d11n_encchspec() argument
43 if (ch->bw == BRCMU_CHAN_BW_20) in brcmu_d11n_encchspec()
44 ch->sb = BRCMU_CHAN_SB_NONE; in brcmu_d11n_encchspec()
46 ch->chspec = 0; in brcmu_d11n_encchspec()
47 brcmu_maskset16(&ch->chspec, BRCMU_CHSPEC_CH_MASK, in brcmu_d11n_encchspec()
48 BRCMU_CHSPEC_CH_SHIFT, ch->chnum); in brcmu_d11n_encchspec()
49 brcmu_maskset16(&ch->chspec, BRCMU_CHSPEC_D11N_SB_MASK, in brcmu_d11n_encchspec()
50 0, d11n_sb(ch->sb)); in brcmu_d11n_encchspec()
51 brcmu_maskset16(&ch->chspec, BRCMU_CHSPEC_D11N_BW_MASK, in brcmu_d11n_encchspec()
52 0, d11n_bw(ch->bw)); in brcmu_d11n_encchspec()
[all …]
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| /linux/drivers/tty/serial/jsm/ |
| H A D | jsm_neo.c | 35 static void neo_set_cts_flow_control(struct jsm_channel *ch) in neo_set_cts_flow_control() argument
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
60 writeb(8, &ch->ch_neo_uart->tfifo); in neo_set_cts_flow_control()
61 ch->ch_t_tlevel = 8; in neo_set_cts_flow_control()
63 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
[all …]
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| /linux/drivers/misc/sgi-xp/ |
| H A D | xpc_channel.c | 27 xpc_process_connect(struct xpc_channel *ch, unsigned long *irq_flags) in xpc_process_connect() argument
31 lockdep_assert_held(&ch->lock); in xpc_process_connect()
33 if (!(ch->flags & XPC_C_OPENREQUEST) || in xpc_process_connect()
34 !(ch->flags & XPC_C_ROPENREQUEST)) { in xpc_process_connect()
38 DBUG_ON(!(ch->flags & XPC_C_CONNECTING)); in xpc_process_connect()
40 if (!(ch->flags & XPC_C_SETUP)) { in xpc_process_connect()
41 spin_unlock_irqrestore(&ch->lock, *irq_flags); in xpc_process_connect()
42 ret = xpc_arch_ops.setup_msg_structures(ch); in xpc_process_connect()
43 spin_lock_irqsave(&ch->lock, *irq_flags); in xpc_process_connect()
46 XPC_DISCONNECT_CHANNEL(ch, ret, irq_flags); in xpc_process_connect()
[all …]
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | vlv_dpio_phy_regs.h | 13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ argument
14 #define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) argument
16 #define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) argument
17 #define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) argument
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
20 #define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4) argument
26 #define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3) argument
47 #define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5) argument
55 #define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7) argument
57 #define VLV_PLL_DW16(ch) _VLV_PLL((ch), 16) argument
[all …]
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| /linux/drivers/clocksource/ |
| H A D | sh_cmt.c | 241 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch) in sh_cmt_read_cmstr() argument
243 if (ch->iostart) in sh_cmt_read_cmstr()
244 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
246 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
249 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value) in sh_cmt_write_cmstr() argument
251 u32 old_value = sh_cmt_read_cmstr(ch); in sh_cmt_write_cmstr()
254 if (ch->iostart) { in sh_cmt_write_cmstr()
255 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
256 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
258 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
[all …]
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| H A D | sh_tmu.c | 84 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
102 return ioread32(ch->base + offs); in sh_tmu_read()
105 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, in sh_tmu_write() argument
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
[all …]
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| H A D | sh_mtu2.c | 156 static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) in sh_mtu2_read() argument
161 return ioread8(ch->mtu->mapbase + 0x280); in sh_mtu2_read()
166 return ioread16(ch->base + offs); in sh_mtu2_read()
168 return ioread8(ch->base + offs); in sh_mtu2_read()
171 static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, in sh_mtu2_write() argument
177 return iowrite8(value, ch->mtu->mapbase + 0x280); in sh_mtu2_write()
182 iowrite16(value, ch->base + offs); in sh_mtu2_write()
184 iowrite8(value, ch->base + offs); in sh_mtu2_write()
187 static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) in sh_mtu2_start_stop_ch() argument
192 raw_spin_lock_irqsave(&ch->mtu->lock, flags); in sh_mtu2_start_stop_ch()
[all …]
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| /linux/include/linux/mfd/ |
| H A D | max5970.h | 19 #define MAX5970_REG_CURRENT_L(ch) (0x01 + (ch) * 4) argument
20 #define MAX5970_REG_CURRENT_H(ch) (0x00 + (ch) * 4) argument
21 #define MAX5970_REG_VOLTAGE_L(ch) (0x03 + (ch) * 4) argument
22 #define MAX5970_REG_VOLTAGE_H(ch) (0x02 + (ch) * 4) argument
25 #define MAX5970_MON(reg, ch) (((reg) >> ((ch) * 2)) & MAX5970_MON_MASK) argument
28 #define MAX5970_REG_CH_UV_WARN_H(ch) (0x1A + (ch) * 10) argument
29 #define MAX5970_REG_CH_UV_WARN_L(ch) (0x1B + (ch) * 10) argument
30 #define MAX5970_REG_CH_UV_CRIT_H(ch) (0x1C + (ch) * 10) argument
31 #define MAX5970_REG_CH_UV_CRIT_L(ch) (0x1D + (ch) * 10) argument
32 #define MAX5970_REG_CH_OV_WARN_H(ch) (0x1E + (ch) * 10) argument
[all …]
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| /linux/drivers/gpu/drm/imx/dcss/ |
| H A D | dcss-dpr.c | 118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
123 struct dcss_dpr *dpr = ch->dpr; in dcss_dpr_write()
125 dcss_ctxld_write(dpr->ctxld, dpr->ctx_id, val, ch->base_ofs + ofs); in dcss_dpr_write()
130 struct dcss_dpr_ch *ch; in dcss_dpr_ch_init_all() local
134 ch = &dpr->ch[i]; in dcss_dpr_ch_init_all()
136 ch->base_ofs = dpr_base + i * 0x1000; in dcss_dpr_ch_init_all()
138 ch->base_reg = devm_ioremap(dpr->dev, ch->base_ofs, SZ_4K); in dcss_dpr_ch_init_all()
139 if (!ch->base_reg) { in dcss_dpr_ch_init_all()
140 dev_err(dpr->dev, "dpr: unable to remap ch %d base\n", in dcss_dpr_ch_init_all()
[all …]
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| H A D | dcss-scaler.c | 90 struct dcss_scaler_ch ch[3]; member
287 static void dcss_scaler_write(struct dcss_scaler_ch *ch, u32 val, u32 ofs) in dcss_scaler_write() argument
289 struct dcss_scaler *scl = ch->scl; in dcss_scaler_write()
291 dcss_ctxld_write(scl->ctxld, scl->ctx_id, val, ch->base_ofs + ofs); in dcss_scaler_write()
297 struct dcss_scaler_ch *ch; in dcss_scaler_ch_init_all() local
301 ch = &scl->ch[i]; in dcss_scaler_ch_init_all()
303 ch->base_ofs = scaler_base + i * 0x400; in dcss_scaler_ch_init_all()
305 ch->base_reg = devm_ioremap(scl->dev, ch->base_ofs, SZ_4K); in dcss_scaler_ch_init_all()
306 if (!ch->base_reg) { in dcss_scaler_ch_init_all()
307 dev_err(scl->dev, "scaler: unable to remap ch base\n"); in dcss_scaler_ch_init_all()
[all …]
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| /linux/drivers/dma/ |
| H A D | moxart-dma.c | 180 struct moxart_chan *ch = to_moxart_dma_chan(chan); in moxart_terminate_all() local
185 dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch); in moxart_terminate_all()
187 spin_lock_irqsave(&ch->vc.lock, flags); in moxart_terminate_all()
189 if (ch->desc) { in moxart_terminate_all()
190 moxart_dma_desc_free(&ch->desc->vd); in moxart_terminate_all()
191 ch->desc = NULL; in moxart_terminate_all()
194 ctrl = readl(ch->base + REG_OFF_CTRL); in moxart_terminate_all()
196 writel(ctrl, ch->base + REG_OFF_CTRL); in moxart_terminate_all()
198 vchan_get_all_descriptors(&ch->vc, &head); in moxart_terminate_all()
199 spin_unlock_irqrestore(&ch->vc.lock, flags); in moxart_terminate_all()
[all …]
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| /linux/drivers/s390/net/ |
| H A D | ctcm_fsms.c | 188 * ch : The channel, the error belongs to.
191 void ctcm_ccw_check_rc(struct channel *ch, int rc, char *msg) in ctcm_ccw_check_rc() argument
195 CTCM_FUNTAIL, ch->id, msg, rc); in ctcm_ccw_check_rc()
199 ch->id); in ctcm_ccw_check_rc()
200 fsm_event(ch->fsm, CTC_EVENT_IO_EBUSY, ch); in ctcm_ccw_check_rc()
204 ch->id); in ctcm_ccw_check_rc()
205 fsm_event(ch->fsm, CTC_EVENT_IO_ENODEV, ch); in ctcm_ccw_check_rc()
210 fsm_event(ch->fsm, CTC_EVENT_IO_UNKNOWN, ch); in ctcm_ccw_check_rc()
248 struct channel *ch = arg; in chx_txdone() local
249 struct net_device *dev = ch->netdev; in chx_txdone()
[all …]
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| H A D | ctcm_main.c | 72 * ch The channel where this skb has been received.
75 void ctcm_unpack_skb(struct channel *ch, struct sk_buff *pskb) in ctcm_unpack_skb() argument
77 struct net_device *dev = ch->netdev; in ctcm_unpack_skb()
91 if ((ch->protocol == CTCM_PROTO_S390) && in ctcm_unpack_skb()
93 if (!(ch->logflags & LOG_FLAG_ILLEGALPKT)) { in ctcm_unpack_skb()
94 ch->logflags |= LOG_FLAG_ILLEGALPKT; in ctcm_unpack_skb()
113 if (!(ch->logflags & LOG_FLAG_ILLEGALSIZE)) { in ctcm_unpack_skb()
119 ch->logflags |= LOG_FLAG_ILLEGALSIZE; in ctcm_unpack_skb()
130 if (!(ch->logflags & LOG_FLAG_OVERRUN)) { in ctcm_unpack_skb()
135 ch->logflags |= LOG_FLAG_OVERRUN; in ctcm_unpack_skb()
[all …]
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| /linux/drivers/isdn/mISDN/ |
| H A D | hwchannel.c | 46 if (likely(bch->ch.peer)) { in bchannel_bh()
47 err = bch->ch.recv(bch->ch.peer, skb); in bchannel_bh()
57 mISDN_initdchannel(struct dchannel *ch, int maxlen, void *phf) in mISDN_initdchannel() argument
59 test_and_set_bit(FLG_HDLC, &ch->Flags); in mISDN_initdchannel()
60 ch->maxlen = maxlen; in mISDN_initdchannel()
61 ch->hw = NULL; in mISDN_initdchannel()
62 ch->rx_skb = NULL; in mISDN_initdchannel()
63 ch->tx_skb = NULL; in mISDN_initdchannel()
64 ch->tx_idx = 0; in mISDN_initdchannel()
65 ch->phfunc = phf; in mISDN_initdchannel()
[all …]
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| H A D | stack.c | 36 mISDN_queue_message(struct mISDNchannel *ch, struct sk_buff *skb) in mISDN_queue_message() argument
38 _queue_message(ch->st, skb); in mISDN_queue_message()
45 struct mISDNchannel *ch; in get_channel4id() local
48 list_for_each_entry(ch, &st->layer2, list) { in get_channel4id()
49 if (id == ch->nr) in get_channel4id()
52 ch = NULL; in get_channel4id()
55 return ch; in get_channel4id()
86 struct mISDNchannel *ch; in send_layer2() local
93 list_for_each_entry(ch, &st->layer2, list) { in send_layer2()
94 if (list_is_last(&ch->list, &st->layer2)) { in send_layer2()
[all …]
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| /linux/drivers/video/fbdev/ |
| H A D | sh_mobile_lcdcfb.c | 213 struct sh_mobile_lcdc_chan ch[2]; member
398 struct sh_mobile_lcdc_chan *ch = handle; in lcdc_sys_write_index() local
400 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT); in lcdc_sys_write_index()
401 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); in lcdc_sys_write_index()
402 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | in lcdc_sys_write_index()
403 (lcdc_chan_is_sublcd(ch) ? 2 : 0)); in lcdc_sys_write_index()
404 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); in lcdc_sys_write_index()
409 struct sh_mobile_lcdc_chan *ch = handle; in lcdc_sys_write_data() local
411 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW); in lcdc_sys_write_data()
412 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); in lcdc_sys_write_data()
[all …]
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| /linux/drivers/rapidio/ |
| H A D | rio_cm.c | 222 static int riocm_ch_close(struct rio_channel *ch);
244 static int riocm_cmp(struct rio_channel *ch, enum rio_cm_state cmp) in riocm_cmp() argument
248 spin_lock_bh(&ch->lock); in riocm_cmp()
249 ret = (ch->state == cmp); in riocm_cmp()
250 spin_unlock_bh(&ch->lock); in riocm_cmp()
254 static int riocm_cmp_exch(struct rio_channel *ch, in riocm_cmp_exch() argument
259 spin_lock_bh(&ch->lock); in riocm_cmp_exch()
260 ret = (ch->state == cmp); in riocm_cmp_exch()
262 ch->state = exch; in riocm_cmp_exch()
263 spin_unlock_bh(&ch->lock); in riocm_cmp_exch()
[all …]
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| /linux/sound/soc/codecs/ |
| H A D | rk3308_codec.h | 24 #define RK3308_ADC_DIG_OFFSET(ch) (((ch) & 0x3) * 0xc0 + 0x0) argument
26 #define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x04) argument
27 #define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x08) argument
28 #define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x0c) argument
29 #define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x10) argument
30 #define RK3308_ADC_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x14) // ver.C only argument
31 #define RK3308_ADC_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x18) // ver.C only argument
32 #define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x1c) argument
34 #define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x40) argument
35 #define RK3308_ALC_L_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x44) argument
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| H A D | idt821034.c | 38 } ch[IDT821034_NB_CHANNEL]; member
44 } ch[IDT821034_NB_CHANNEL]; member
119 static int idt821034_set_channel_power(struct idt821034 *idt821034, u8 ch, u8 power) in idt821034_set_channel_power() argument
124 dev_dbg(&idt821034->spi->dev, "set_channel_power(%u, 0x%x)\n", ch, power); in idt821034_set_channel_power()
126 conf = IDT821034_MODE_CODEC(ch) | idt821034->cache.codec_conf; in idt821034_set_channel_power()
131 idt821034->cache.ch[ch].rx_slot); in idt821034_set_channel_power()
138 idt821034->cache.ch[ch].tx_slot); in idt821034_set_channel_power()
148 idt821034->cache.ch[ch].power = power; in idt821034_set_channel_power()
153 static u8 idt821034_get_channel_power(struct idt821034 *idt821034, u8 ch) in idt821034_get_channel_power() argument
155 return idt821034->cache.ch[ch].power; in idt821034_get_channel_power()
[all …]
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| /linux/drivers/gpu/ipu-v3/ |
| H A D | ipu-cpmem.c | 93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
126 static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs) in ipu_ch_param_read_field() argument
128 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_read_field()
228 void ipu_cpmem_zero(struct ipuv3_channel *ch) in ipu_cpmem_zero() argument
230 struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch); in ipu_cpmem_zero()
239 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres) in ipu_cpmem_set_resolution() argument
[all …]
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| /linux/drivers/net/ethernet/ |
| H A D | lantiq_xrx200.c | 130 static void xrx200_flush_dma(struct xrx200_chan *ch) in xrx200_flush_dma() argument
135 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; in xrx200_flush_dma()
141 ch->priv->rx_buf_size; in xrx200_flush_dma()
142 ch->dma.desc++; in xrx200_flush_dma()
143 ch->dma.desc %= LTQ_DESC_NUM; in xrx200_flush_dma()
187 static int xrx200_alloc_buf(struct xrx200_chan *ch, void *(*alloc)(unsigned int size)) in xrx200_alloc_buf() argument
189 void *buf = ch->rx_buff[ch->dma.desc]; in xrx200_alloc_buf()
190 struct xrx200_priv *priv = ch->priv; in xrx200_alloc_buf()
194 ch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size); in xrx200_alloc_buf()
195 if (!ch->rx_buff[ch->dma.desc]) { in xrx200_alloc_buf()
[all …]
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| /linux/drivers/gpu/host1x/hw/ |
| H A D | cdma_hw.c | 45 struct host1x_channel *ch = cdma_to_channel(cdma); in cdma_start() local
55 host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, in cdma_start()
59 host1x_ch_writel(ch, lower_32_bits(start), HOST1X_CHANNEL_DMASTART); in cdma_start()
61 host1x_ch_writel(ch, upper_32_bits(start), HOST1X_CHANNEL_DMASTART_HI); in cdma_start()
63 host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT); in cdma_start()
65 host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMAPUT_HI); in cdma_start()
67 host1x_ch_writel(ch, lower_32_bits(end), HOST1X_CHANNEL_DMAEND); in cdma_start()
69 host1x_ch_writel(ch, upper_32_bits(end), HOST1X_CHANNEL_DMAEND_HI); in cdma_start()
73 host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP | in cdma_start()
79 host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMACTRL); in cdma_start()
[all …]
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| /linux/drivers/net/wireless/realtek/rtw89/ |
| H A D | phy_be.c | 566 u8 band, u8 bw, u8 ntx, u8 rs, u8 ch) in fill_limit_nonbf_bf() argument
572 rs, bf, ch); in fill_limit_nonbf_bf()
592 u8 band, u8 ntx, u8 ch) in phy_fill_limit_20m_be() argument
595 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_CCK, ch); in phy_fill_limit_20m_be()
597 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_CCK, ch); in phy_fill_limit_20m_be()
599 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_OFDM, ch); in phy_fill_limit_20m_be()
601 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_MCS, ch); in phy_fill_limit_20m_be()
606 u8 band, u8 ntx, u8 ch, u8 pri_ch) in phy_fill_limit_40m_be() argument
609 RTW89_CHANNEL_WIDTH_20, ntx, RTW89_RS_CCK, ch - 2); in phy_fill_limit_40m_be()
611 RTW89_CHANNEL_WIDTH_40, ntx, RTW89_RS_CCK, ch); in phy_fill_limit_40m_be()
[all …]
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| /linux/arch/sparc/include/asm/ |
| H A D | chafsr.h | 9 * ch --> cheetah
10 * ch+ --> cheetah plus
26 #define CHPAFSR_DTO (1UL << 59UL) /* ch+ */
31 #define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */
34 #define CHPAFSR_THCE (1UL << 57UL) /* ch+ */
39 #define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */
44 #define CHPAFSR_TUE (1UL << 55UL) /* ch+ */
51 #define CHPAFSR_DUE (1UL << 54UL) /* ch+ */
69 #define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */
74 #define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */
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| /linux/drivers/dma/dw-edma/ |
| H A D | dw-hdma-v0-debugfs.c | 28 __ch_regs = REGS_ADDR(dw, ch[_ch].rd); \
30 __ch_regs = REGS_ADDR(dw, ch[_ch].wr); \
35 #define CTX_REGISTER(dw, name, dir, ch) \ argument
36 {#name, REGS_CH_ADDR(dw, name, dir, ch)}
80 u16 ch, struct dentry *dent) in dw_hdma_debugfs_regs_ch() argument
83 CTX_REGISTER(dw, ch_en, dir, ch), in dw_hdma_debugfs_regs_ch()
84 CTX_REGISTER(dw, doorbell, dir, ch), in dw_hdma_debugfs_regs_ch()
85 CTX_REGISTER(dw, prefetch, dir, ch), in dw_hdma_debugfs_regs_ch()
86 CTX_REGISTER(dw, handshake, dir, ch), in dw_hdma_debugfs_regs_ch()
87 CTX_REGISTER(dw, llp.lsb, dir, ch), in dw_hdma_debugfs_regs_ch()
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