| /linux/drivers/net/ethernet/neterion/ |
| H A D | s2io.c | 1010 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_verify_pci_mode() local
1014 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1044 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_print_pci_mode() local
1050 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1114 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_tti() local
1138 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1163 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1168 writeq(val64, &bar0->tti_command_mem); in init_tti()
1170 if (wait_for_cmd_complete(&bar0->tti_command_mem, in init_tti()
1190 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_nic() local
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| /linux/drivers/gpu/nova-core/fb/hal/ |
| H A D | tu102.rs | 3 use crate::driver::Bar0;
12 pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 { in read_sysmem_flush_page_gm107()
16 pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page_gm107() argument
29 pub(super) fn display_enabled_gm107(bar: &Bar0) -> bool { in display_enabled_gm107()
33 pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 { in vidmem_size_gp102()
40 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { in read_sysmem_flush_page()
44 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page() argument
48 fn supports_display(&self, bar: &Bar0) -> bool { in supports_display()
52 fn vidmem_size(&self, bar: &Bar0) -> u64 { in vidmem_size()
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| H A D | ga100.rs | 7 use crate::driver::Bar0;
13 pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 { in read_sysmem_flush_page_ga100()
19 pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) { in write_sysmem_flush_page_ga100() argument
28 pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool { in display_enabled_ga100()
37 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { in read_sysmem_flush_page()
41 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page() argument
47 fn supports_display(&self, bar: &Bar0) -> bool { in supports_display()
51 fn vidmem_size(&self, bar: &Bar0) -> u64 { in vidmem_size()
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| H A D | ga102.rs | 5 use crate::driver::Bar0;
9 fn vidmem_size_ga102(bar: &Bar0) -> u64 { in vidmem_size_ga102()
16 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { in read_sysmem_flush_page()
20 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { in write_sysmem_flush_page() argument
26 fn supports_display(&self, bar: &Bar0) -> bool { in supports_display()
30 fn vidmem_size(&self, bar: &Bar0) -> u64 { in vidmem_size()
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| /linux/sound/pci/lola/ |
| H A D | lola.c | 93 lola_writew(chip, BAR0, CORBWP, wp); in corb_send_verb()
114 wp = lola_readw(chip, BAR0, RIRBWP); in lola_update_rirb()
264 rbsts = lola_readb(chip, BAR0, RIRBSTS); in lola_interrupt()
267 lola_writeb(chip, BAR0, RIRBSTS, rbsts); in lola_interrupt()
268 rbsts = lola_readb(chip, BAR0, CORBSTS); in lola_interrupt()
271 lola_writeb(chip, BAR0, CORBSTS, rbsts); in lola_interrupt()
297 unsigned int gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
307 lola_writel(chip, BAR0, GCTL, LOLA_GCTL_RESET); in reset_controller()
311 gctl = lola_readl(chip, BAR0, GCTL); in reset_controller()
361 lola_writeb(chip, BAR0, RIRBCTL, 0); in setup_corb_rirb()
[all …]
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| /linux/Documentation/misc-devices/ |
| H A D | spear-pcie-gadget.rst | 46 bar0_size: returns size of bar0 in hex.
47 bar0_address returns address of bar0 mapped area in hex.
48 bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
65 bar0_size write size of bar0 in hex. default bar0 size is 1000 (hex)
67 bar0_address write address of bar0 mapped area in hex. (default mapping of
68 bar0 is SYSRAM1(E0800000). Always program bar size before bar
71 bar0_rw_offset write offset of bar0 for which bar0_data will write value.
98 program BAR0 size as 1MB::
102 check for programmed bar0 size::
106 Program BAR0 Address as DDR (0x2100000). This is the physical address of
[all …]
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| /linux/drivers/gpu/nova-core/fb/ |
| H A D | hal.rs | 5 use crate::driver::Bar0;
14 fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64; in read_sysmem_flush_page()
19 fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result; in write_sysmem_flush_page() argument
22 fn supports_display(&self, bar: &Bar0) -> bool; in supports_display()
25 fn vidmem_size(&self, bar: &Bar0) -> u64; in vidmem_size()
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| /linux/drivers/gpu/nova-core/falcon/hal/ |
| H A D | ga102.rs | 9 use crate::driver::Bar0;
18 fn select_core_ga102<E: FalconEngine>(bar: &Bar0) -> Result { in select_core_ga102()
41 bar: &Bar0, in signature_reg_fuse_version_ga102() argument
76 fn program_brom_ga102<E: FalconEngine>(bar: &Bar0, params: &FalconBromParams) -> Result { in program_brom_ga102() argument
102 fn select_core(&self, _falcon: &Falcon<E>, bar: &Bar0) -> Result { in select_core()
109 bar: &Bar0, in signature_reg_fuse_version() argument
116 fn program_brom(&self, _falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result { in program_brom() argument
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| /linux/drivers/platform/x86/ |
| H A D | p2sb.c | 33 * Cache BAR0 of P2SB device functions 0 to 7.
68 struct resource *bar0 = pci_resource_n(pdev, 0); in p2sb_read_bar0() local
78 mem->start = bar0->start; in p2sb_read_bar0()
79 mem->end = bar0->end; in p2sb_read_bar0()
80 mem->flags = bar0->flags; in p2sb_read_bar0()
81 mem->desc = bar0->desc; in p2sb_read_bar0()
107 /* Scan the P2SB device and cache its BAR0 */ in p2sb_scan_and_cache()
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| /linux/drivers/gpu/nova-core/falcon/ |
| H A D | hal.rs | 5 use crate::driver::Bar0;
18 fn select_core(&self, _falcon: &Falcon<E>, _bar: &Bar0) -> Result { in select_core()
27 bar: &Bar0, in signature_reg_fuse_version() argument
33 fn program_brom(&self, falcon: &Falcon<E>, bar: &Bar0, params: &FalconBromParams) -> Result; in program_brom() argument
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| H A D | gsp.rs | 4 driver::Bar0,
19 pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { in clear_swgen0_intr() argument
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| /linux/Documentation/scsi/ |
| H A D | hptiop.rst | 11 For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
14 BAR0 offset Register
36 For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
39 BAR0 offset Register
54 For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
57 BAR0 offset Register
78 For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
81 BAR0 offset Register
119 relative to the IOP BAR0.
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| /linux/drivers/net/mdio/ |
| H A D | mdio-thunder.c | 18 void __iomem *bar0; member
49 nexus->bar0 = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); in thunder_mdiobus_pci_probe()
50 if (!nexus->bar0) { in thunder_mdiobus_pci_probe()
86 bus->register_base = nexus->bar0 + in thunder_mdiobus_pci_probe()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | shadowramin.c | 27 u32 bar0; member
49 nvkm_wr32(device, 0x001700, priv->bar0); in pramin_fini()
104 /* modify bar0 PRAMIN window to cover the bios image */ in pramin_init()
111 priv->bar0 = nvkm_rd32(device, 0x001700); in pramin_init()
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| /linux/drivers/gpu/nova-core/ |
| H A D | fb.rs | 11 use crate::driver::Bar0;
44 bar: &Bar0, in register() argument
62 pub(crate) fn unregister(&self, bar: &Bar0) { in unregister() argument
96 pub(crate) fn new(chipset: Chipset, bar: &Bar0) -> Result<Self> { in new()
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| H A D | falcon.rs | 14 use crate::driver::Bar0;
343 bar: &Bar0, in new() argument
369 fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result { in reset_wait_mem_scrubbing()
381 fn reset_eng(&self, bar: &Bar0) -> Result { in reset_eng()
409 pub(crate) fn reset(&self, bar: &Bar0) -> Result { in reset()
427 bar: &Bar0, in dma_wr() argument
504 pub(crate) fn dma_load<F: FalconFirmware<Target = E>>(&self, bar: &Bar0, fw: &F) -> Result { in dma_load() argument
534 bar: &Bar0, in boot() argument
581 bar: &Bar0, in signature_reg_fuse_version() argument
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| H A D | gpu.rs | 5 use crate::driver::Bar0;
155 fn new(bar: &Bar0) -> Result<Spec> { in new()
170 bar: Arc<Devres<Bar0>>,
195 bar: &Bar0, in run_fwsec_frts() argument
268 devres_bar: Arc<Devres<Bar0>>, in new() argument
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| H A D | driver.rs | 15 pub(crate) type Bar0 = pci::Bar<BAR0_SIZE>; typedef
38 pdev.iomap_region_sized::<BAR0_SIZE>(0, c_str!("nova-core/bar0")), in probe()
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| /linux/include/linux/usb/ |
| H A D | net2280.h | 24 /* main registers, BAR0 + 0x0000 */
227 /* usb control, BAR0 + 0x0080 */
291 /* pci control, BAR0 + 0x0100 */
318 /* dma control, BAR0 + 0x0180 ... array of four structs like this,
360 /* dedicated endpoint registers, BAR0 + 0x0200 */
370 /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
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| /linux/drivers/net/ethernet/broadcom/bnge/ |
| H A D | bnge_core.c | 197 if (bd->bar0) { in bnge_unmap_bars()
198 pci_iounmap(pdev, bd->bar0); in bnge_unmap_bars()
199 bd->bar0 = NULL; in bnge_unmap_bars()
261 bd->bar0 = pci_ioremap_bar(pdev, 0); in bnge_probe_one()
262 if (!bd->bar0) { in bnge_probe_one()
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| /linux/samples/rust/ |
| H A D | rust_driver_pci.rs | 19 type Bar0 = pci::Bar<{ Regs::END }>; typedef
32 bar: Devres<Bar0>,
47 fn testdev(index: &TestIndex, bar: &Bar0) -> Result<u32> { in testdev()
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| /linux/drivers/scsi/snic/ |
| H A D | snic_main.c | 260 if (snic->bar0.vaddr) in snic_iounmap()
261 iounmap(snic->bar0.vaddr); in snic_iounmap()
428 /* Map vNIC resources from BAR0 */ in snic_probe()
430 SNIC_HOST_ERR(shost, "BAR0 not memory mappable aborting.\n"); in snic_probe()
436 snic->bar0.vaddr = pci_iomap(pdev, 0, 0); in snic_probe()
437 if (!snic->bar0.vaddr) { in snic_probe()
439 "Cannot memory map BAR0 res hdr aborting.\n"); in snic_probe()
445 snic->bar0.bus_addr = pci_resource_start(pdev, 0); in snic_probe()
446 snic->bar0.len = pci_resource_len(pdev, 0); in snic_probe()
447 SNIC_BUG_ON(snic->bar0.bus_addr == 0); in snic_probe()
[all …]
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| /linux/drivers/net/ethernet/qlogic/qlcnic/ |
| H A D | qlcnic_hw.h | 37 /* Read from an address offset from BAR0, existing registers */
41 /* Write to an address offset from BAR0, existing registers */
45 /* Read from a direct address offset from BAR0, additional registers */
49 /* Write to a direct address offset from BAR0, additional registers */
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| /linux/drivers/infiniband/hw/usnic/ |
| H A D | usnic_vnic.c | 97 struct vnic_dev_bar *bar0; in usnic_vnic_dump() local
101 bar0 = usnic_vnic_get_bar(vnic, 0); in usnic_vnic_dump()
103 "VF:%hu BAR0 bus_addr=%pa vaddr=0x%p size=%ld ", in usnic_vnic_dump()
105 &bar0->bus_addr, in usnic_vnic_dump()
106 bar0->vaddr, bar0->len); in usnic_vnic_dump()
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| /linux/arch/x86/kernel/ |
| H A D | early_printk.c | 267 u32 classcode, bar0; in early_pci_serial_init() local
309 bar0 = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0); in early_pci_serial_init()
324 if ((bar0 & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { in early_pci_serial_init()
326 early_serial_base = bar0 & PCI_BASE_ADDRESS_IO_MASK; in early_pci_serial_init()
335 (unsigned long)early_ioremap(bar0 & PCI_BASE_ADDRESS_MEM_MASK, 0x10); in early_pci_serial_init()
337 kexec_debug_8250_mmio32 = bar0 & PCI_BASE_ADDRESS_MEM_MASK; in early_pci_serial_init()
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