Searched full:altera (Results 1 – 25 of 230) sorted by relevance
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16 tristate "Altera SOCFPGA FPGA Manager"19 FPGA manager driver support for Altera SOCFPGA.22 tristate "Altera SoCFPGA Arria10"26 FPGA manager driver support for Altera Arria10 SoCFPGA.29 tristate "Altera Partial Reconfiguration IP Core"31 Core driver support for Altera Partial Reconfiguration IP component34 tristate "Platform support of Altera Partial Reconfiguration IP Core"37 Platform driver support for Altera Partial Reconfiguration IP41 tristate "Altera FPGA Passive Serial over SPI"45 FPGA manager driver support for Altera Arria/Cyclone/Stratix[all …]
10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o25 obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o26 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o33 obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o34 obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
3 * Driver for Altera Partial Reconfiguration IP Core7 * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation8 * by Alan Tull <atull@opensource.altera.com>10 #include <linux/fpga/altera-pr-ip-core.h>45 MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Platform Driver");
3 * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters13 * This driver manages bridges on a Altera SOCFPGA between the ARM host217 MODULE_DESCRIPTION("Altera SoCFPGA HPS to FPGA Bridge");218 MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
3 * Driver for Altera Partial Reconfiguration IP Core7 * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation8 * by Alan Tull <atull@opensource.altera.com>11 #include <linux/fpga/altera-pr-ip-core.h>200 MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.170 MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");171 MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
402 bool "Altera SOCFPGA ECC"406 Altera SOCs. This is the global enable for the407 various Altera peripherals.410 bool "Altera SDRAM ECC"414 Altera SDRAM Memory for Altera SoCs. Note that the419 bool "Altera L2 Cache ECC"423 Altera L2 cache Memory for Altera SoCs. This option427 bool "Altera On-Chip RAM ECC"431 Altera On-Chip RAM Memory for Altera SoCs.434 bool "Altera Ethernet FIFO ECC"[all …]
2 altera-stapl-y = altera-jtag.o altera-comp.o altera.o3 altera-stapl-$(CONFIG_HAS_IOPORT) += altera-lpt.o5 obj-$(CONFIG_ALTERA_STAPL) += altera-stapl.o
3 * altera-lpt.c5 * altera FPGA driver7 * Copyright (C) Altera Corporation 1998-200114 #include "altera-exprt.h"
2 comment "Altera FPGA firmware download module (requires I2C)"6 tristate "Altera FPGA firmware download module"9 An Altera FPGA module. Say Y when you want to support this tool.
3 * altera-exprt.h5 * altera FPGA driver7 * Copyright (C) Altera Corporation 1998-2001
3 * altera-comp.c5 * altera FPGA driver7 * Copyright (C) Altera Corporation 1998-200113 #include "altera-exprt.h"
3 * altera-jtag.h5 * altera FPGA driver7 * Copyright (C) Altera Corporation 1998-2001
6 Altera Triple-Speed Ethernet MAC driver9 Copyright |copy| 2008-2014 Altera Corporation11 This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers19 For more information visit www.altera.com and www.rocketboards.org. Support25 components that can be assembled and built into an FPGA using the Altera44 visit www.altera.com for known, documented SGDMA errata.61 Altera Triple-Speed Ethernet MAC support (ALTERA_TSE)147 RFC defined statistics, and driver or Altera defined statistics. The four154 - Altera Triple Speed Ethernet User Guide, found at http://www.altera.com274 Altera TSE. This statistics counts the number of received good and errored[all …]
5 * GPIO driver for Altera Arria10 MAX5 System Resource Chip11 #include <linux/mfd/altera-a10sr.h>17 * struct altr_a10sr_gpio - Altera Max5 GPIO device private data structure114 MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>");115 MODULE_DESCRIPTION("Altera Arria10 System Resource Chip GPIO");
3 * DMA driver for Altera mSGDMA IP core206 * @mdev: Pointer to the Altera mSGDMA device structure227 * @mdev: Pointer to the Altera mSGDMA device structure245 * @mdev: Pointer to the Altera mSGDMA device structure531 * @mdev: Pointer to the Altera mSGDMA device structure547 * @mdev: Pointer to the Altera mSGDMA device structure581 * @mdev: Pointer to the Altera mSGDMA device structure606 * @mdev: Pointer to the Altera mSGDMA device structure623 * @mdev: Pointer to the Altera mSGDMA device structure680 * @t: Pointer to the Altera sSGDMA channel structure[all …]
3 * Driver for Altera Partial Reconfiguration IP Core7 * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation8 * by Alan Tull <atull@opensource.altera.com>
3 * altera.h5 * altera FPGA driver7 * Copyright (C) Altera Corporation 1998-2001
1 Altera Passive Serial SPI FPGA Manager3 Altera FPGAs support a method of loading the bitstream over what is8 See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
1 * Altera I2C Controller2 * This is Altera's synthesizable logic block I2C Controller for use3 * in Altera's FPGAs.
55 tristate "Altera FPGA based CI module"59 An Altera FPGA CI module for NetUP Dual DVB-T/C RF CI card.62 module will be called altera-ci
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>10 model = "Altera SOCFPGA VT";
3 * Altera PCIe MSI support5 * Author: Ley Foon Tan <lftan@altera.com>7 * Copyright Altera Corporation (C) 2013-2015. All rights reserved78 .name = "Altera PCIe MSI",109 .name = "Altera MSI",273 .name = "altera-msi",
3 * Altera Arria10 DevKit System Resource MFD Driver5 * Author: Thor Thayer <tthayer@opensource.altera.com>9 * SPI access for Altera Arria10 MAX5 System Resource Chip14 #include <linux/mfd/altera-a10sr.h>
3 * altera_jtaguart.c -- Altera JTAG UART driver30 * Altera JTAG UART register definitions according to the Altera JTAG UART31 * datasheet: https://www.altera.com/literature/hb/nios2/n2cpu_nii51009.pdf178 pr_err(DRV_NAME ": unable to attach Altera JTAG UART %d " in altera_jtaguart_startup()213 return (port->type == PORT_ALTERA_JTAGUART) ? "Altera JTAG UART" : NULL; in altera_jtaguart_type()481 MODULE_DESCRIPTION("Altera JTAG UART driver");