Searched full:adjustable (Results 1 – 25 of 64) sorted by relevance
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49 This is adjustable via64 This is adjustable via83 This is adjustable via102 This is adjustable via120 This is adjustable via136 This is adjustable via
7 * Adjustable divider clock implementation16 * DOC: basic adjustable divider clock that cannot gate21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)32 * struct zynqmp_clk_divider - adjustable divider clock
13 * DOC: basic adjustable multiplexer clock that cannot gate19 * parent - parent is adjustable through clk_set_parent
378 * @fixed_rate: non-adjustable clock rate391 * @fixed_rate: non-adjustable clock rate403 * @fixed_rate: non-adjustable clock rate416 * @fixed_rate: non-adjustable clock rate430 * @fixed_rate: non-adjustable clock rate431 * @fixed_accuracy: non-adjustable clock accuracy446 * @fixed_rate: non-adjustable clock rate447 * @fixed_accuracy: non-adjustable clock accuracy461 * @fixed_rate: non-adjustable clock rate462 * @fixed_accuracy: non-adjustable clock accuracy[all …]
5 * Adjustable factor-based clock implementation19 * DOC: basic adjustable factor-based clock24 * rate - rate is adjustable.
6 register-mapped adjustable clock rate divider that does not gate and has59 - reg : offset for register controlling adjustable divider
11 an adjustable clock rate divider, this behaves exactly as [3]
42 - reg : register offset for register controlling adjustable mux
242 If you have a LCD backlight adjustable by PWM, say Y to enable444 If you have a LCD backlight adjustable by GPIO, say Y to enable476 If you have a LCD backlight adjustable by LED class driver, say Y
15 this value is adjustable depending on platform.
393 #define MWIFIEX_MEF_MAX_BYTESEQ 6 /* non-adjustable */441 #define MWIFIEX_COALESCE_MAX_BYTESEQ 4 /* non-adjustable */
18 * DOC: basic adjustable multiplexer clock that cannot gate24 * parent - parent is adjustable through clk_set_parent
7 * Adjustable divider clock implementation20 * DOC: basic adjustable divider clock that cannot gate25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
20 adjustable conversion time, and averaging function are also built in for
16 * rate - rate is adjustable.22 * rate - rate is adjustable.28 * rate - rate is adjustable.
20 _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
24 Each vcpu has an adjustable guest_halt_poll_ns
89 - FF_GAIN gain is adjustable90 - FF_AUTOCENTER autocenter is adjustable
29 temperature sensors. Each PWM output is individually adjustable and
55 * struct imx_icc_node_adj - Describe a dynamic adjustable node
200 __u32 dmode_extra; /* adjustable bus settings */201 __u32 dcntl_extra; /* adjustable bus settings */202 __u32 ctest7_extra; /* adjustable bus settings */
22 * Adjustable tx de-emphasis (FFE)
40 * struct sprd_pll - definition of adjustable pll clock
60 * struct clk_regmap_div_data - regmap backed adjustable divider specific data