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/linux-6.15/drivers/gpu/drm/tegra/
Ddc.h178 #define SYNCPT_CNTRL_NO_STALL (1 << 8)
191 #define SYNCPT_VSYNC_ENABLE (1 << 8)
204 #define PW4_ENABLE (1 << 8)
220 #define WIN_A_UF_INT (1 << 8)
248 #define GENERAL_UPDATE (1 << 8)
298 #define UNDERFLOW_MODE_RED (1 << 8)
302 #define H_PULSE0_ENABLE (1 << 8)
319 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
325 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
379 #define PULSE_LAST_START_A (0 << 8)
[all …]
/linux-6.15/fs/isofs/
Drock.h15 __u8 extent[8];
16 __u8 offset[8];
17 __u8 size[8];
33 __u8 mode[8];
34 __u8 n_links[8];
35 __u8 uid[8];
36 __u8 gid[8];
40 __u8 dev_high[8];
41 __u8 dev_low[8];
61 __u8 location[8];
[all …]
/linux-6.15/arch/arc/lib/
Dmemset-archs.S46 ;;; if length < 8
47 brls.d.nt r2, 8, .Lsmallchunk
60 asl r4, r1, 8
66 sub3 lp_count, r2, 8
70 add3.hi r2, r2, 8
80 std.ab r4, [r3, 8]
81 std.ab r4, [r3, 8]
82 std.ab r4, [r3, 8]
83 std.ab r4, [r3, 8]
84 std.ab r4, [r3, 8]
[all …]
/linux-6.15/drivers/pmdomain/mediatek/
Dmt8183-pm-domains.h20 .sram_pdn_bits = GENMASK(11, 8),
55 .sram_pdn_bits = GENMASK(8, 8),
65 .sram_pdn_bits = GENMASK(8, 8),
74 .sram_pdn_bits = GENMASK(8, 8),
83 .sram_pdn_bits = GENMASK(8, 8),
104 .sram_pdn_bits = GENMASK(8, 8),
130 .sram_pdn_bits = GENMASK(9, 8),
161 .sram_pdn_bits = GENMASK(9, 8),
187 .sram_pdn_bits = GENMASK(8, 8),
203 .sram_pdn_bits = GENMASK(11, 8),
[all …]
/linux-6.15/tools/perf/arch/x86/tests/
Dinsn-x86-dat-64.c14 {{0x48, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
16 {{0x66, 0x0f, 0x41, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
20 {{0x48, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
22 {{0x66, 0x0f, 0x44, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
111 "c4 a1 78 90 ac f0 23 01 00 00 \tkmovw 0x123(%rax,%r14,8),%k5",},
115 "c4 a1 78 91 ac f0 23 01 00 00 \tkmovw %k5,0x123(%rax,%r14,8)",},
133 "c4 a1 f8 90 ac f0 23 01 00 00 \tkmovq 0x123(%rax,%r14,8),%k5",},
137 "c4 a1 f8 91 ac f0 23 01 00 00 \tkmovq %k5,0x123(%rax,%r14,8)",},
155 "c4 a1 79 90 ac f0 23 01 00 00 \tkmovb 0x123(%rax,%r14,8),%k5",},
159 "c4 a1 79 91 ac f0 23 01 00 00 \tkmovb %k5,0x123(%rax,%r14,8)",},
[all …]
/linux-6.15/arch/powerpc/crypto/
Daes-spe-keys.S21 stw r14,8(r1); /* save registers */ \
26 lwz r14,8(r1); /* restore registers */ \
43 lbz t1,8(t2); \
46 lbz t1,8(t2); \
47 rlwimi r,t1,8,16,23; \
49 lbz t1,8(t2); \
50 rlwimi r,t1,16,8,15; \
52 lbz t1,8(t2); \
78 LOAD_KEY(r7,r4,8)
82 stw r7,8(r3)
[all …]
Dghashp10-ppc.pl34 $SIZE_T=8;
98 vsldoi $H,$H,$H,8 # twist even more ...
99 vsldoi $xC2,$zero,$xC2,8 # 0xc2.0
100 vsldoi $Hl,$zero,$H,8 # ... and split
101 vsldoi $Hh,$H,$zero,8
140 vsldoi $H,$IN,$IN,8 # twist even more ...
141 vsldoi $xC2,$zero,$xC2,8 # 0xc2.0
142 vsldoi $Hl,$zero,$H,8 # ... and split
143 vsldoi $Hh,$H,$zero,8
159 vsldoi $t0,$Xm,$zero,8
[all …]
/linux-6.15/arch/arm/mach-omap2/
Dsoc.h60 #define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
331 #define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
338 #define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
339 #define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
340 #define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
341 #define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
342 #define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
346 #define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
347 #define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
351 #define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
[all …]
/linux-6.15/arch/mips/include/asm/octeon/
Dcvmx-dpi-defs.h33 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35 … CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36 …ine CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
42 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43 #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
[all …]
/linux-6.15/drivers/media/platform/imagination/
De5010-core-regs.h30 #define JASPER_CORE_REV_CR_JASPER_MINOR_REV_SHIFT (8)
143 #define JASPER_LUMA_QUANTIZATION_TABLE0_CR_LUMA_QUANTIZATION_TABLE_01_SHIFT (8)
152 #define JASPER_LUMA_QUANTIZATION_TABLE1_CR_LUMA_QUANTIZATION_TABLE_05_SHIFT (8)
161 #define JASPER_LUMA_QUANTIZATION_TABLE2_CR_LUMA_QUANTIZATION_TABLE_11_SHIFT (8)
170 #define JASPER_LUMA_QUANTIZATION_TABLE3_CR_LUMA_QUANTIZATION_TABLE_15_SHIFT (8)
175 #define JASPER_LUMA_QUANTIZATION_TABLE4_CR_LUMA_QUANTIZATION_TABLE_21_SHIFT (8)
185 #define JASPER_LUMA_QUANTIZATION_TABLE5_CR_LUMA_QUANTIZATION_TABLE_25_SHIFT (8)
198 #define JASPER_LUMA_QUANTIZATION_TABLE6_CR_LUMA_QUANTIZATION_TABLE_31_SHIFT (8)
211 #define JASPER_LUMA_QUANTIZATION_TABLE7_CR_LUMA_QUANTIZATION_TABLE_35_SHIFT (8)
224 #define JASPER_LUMA_QUANTIZATION_TABLE8_CR_LUMA_QUANTIZATION_TABLE_41_SHIFT (8)
[all …]
/linux-6.15/arch/s390/include/asm/
Dfcx.h42 u32 :8;
74 u32 flags:8;
106 u32 rc:8;
129 u32 format:8;
130 u32 flags:8;
131 u32 cu_state:8;
132 u32 dev_state:8;
133 u32 op_state:8;
163 u32 length:8;
164 u32 flags:8;
[all …]
/linux-6.15/sound/soc/codecs/
Drt5668.h367 #define RT5668_L_VOL_MASK (0x3f << 8)
368 #define RT5668_L_VOL_SFT 8
373 #define RT5668_G_HP (0xf << 8)
374 #define RT5668_G_HP_SFT 8
379 #define RT5668_BST_CBJ_MASK (0xf << 8)
380 #define RT5668_BST_CBJ_SFT 8
394 #define RT5668_POL_FAST_OFF_MASK (0x1 << 8)
395 #define RT5668_POL_FAST_OFF_HIGH (0x1 << 8)
396 #define RT5668_POL_FAST_OFF_LOW (0x0 << 8)
441 #define RT5668_DAC_L1_VOL_MASK (0xff << 8)
[all …]
Dmt6358.h17 #define RG_XO_VOW_EN_SFT 8
26 #define RG_AUD_INTRP_CK_PDN_SFT 8
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
80 #define RG_VOW13M_CK_TST_DIS_SFT 8
82 #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
267 #define AUDIO_DIG_DIG_ID_SFT 8
269 #define AUDIO_DIG_DIG_ID_MASK_SFT (0xff << 8)
278 #define AUDIO_DIG_DIG_MINOR_REV_SFT 8
280 #define AUDIO_DIG_DIG_MINOR_REV_MASK_SFT (0xf << 8)
292 #define AUDIO_DIG_ESP_SFT 8
[all …]
/linux-6.15/arch/arm64/lib/
Dcrc-t10dif-core.S107 * This can be implemented using 8x8 long polynomial multiplication, by
108 * reorganizing the input so that each pairwise 8x8 multiplication
114 * 1 (w0*x1 ^ w1*x0) << 8 ^ | (y0*z1 ^ y1*z0) << 8 ^
121 * 8 w1*x7 << 64 | y1*z7 << 64
128 * and after performing 8x8->16 bit long polynomial multiplication of
158 ext t6.16b, t5.16b, t5.16b, #8
160 pmull t3.8h, t7.8b, t5.8b
161 pmull t4.8h, t7.8b, t6.8b
162 pmull2 t5.8h, t7.16b, t5.16b
163 pmull2 t6.8h, t7.16b, t6.16b
[all …]
/linux-6.15/tools/testing/selftests/bpf/progs/
Dverifier_regalloc.c30 *(u64*)(r10 - 8) = r1; \ in __flag()
32 r2 += -8; \ in __flag()
60 *(u64*)(r10 - 8) = r1; \ in regalloc_negative()
62 r2 += -8; \ in regalloc_negative()
90 *(u64*)(r10 - 8) = r1; \ in __flag()
92 r2 += -8; \ in __flag()
115 __failure __msg("invalid access to map value, value_size=48 off=44 size=8")
122 *(u64*)(r10 - 8) = r1; \ in __flag()
124 r2 += -8; \ in __flag()
153 *(u64*)(r10 - 8) = r1; \ in __flag()
[all …]
/linux-6.15/drivers/net/ethernet/intel/i40e/
Di40e_register.h72 #define I40E_PRTDCB_RETSC_LLTC_SHIFT 8
85 #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8
140 #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8
146 #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8
151 #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
528 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */
529 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
647 #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */
659 #define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER …
663 #define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER …
[all …]
/linux-6.15/drivers/clk/rockchip/
Dclk-rk3188.c70 RK3066_PLL_RATE( 891000000, 8, 594, 2),
76 RK3066_PLL_RATE( 742500000, 8, 495, 2),
89 RK3066_PLL_RATE( 297000000, 2, 198, 8),
90 RK3066_PLL_RATE( 252000000, 1, 84, 8),
91 RK3066_PLL_RATE( 216000000, 1, 72, 8),
92 RK3066_PLL_RATE( 148500000, 2, 99, 8),
103 #define RK3066_DIV_ACLK_HCLK_SHIFT 8
154 .mux_core_shift = 8,
194 .mux_core_shift = 8,
220 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
[all …]
/linux-6.15/arch/x86/crypto/
Dtwofish-i586-asm_32.S16 #define out_blk 8 /* output byte array address parameter*/
21 #define c_offset 8
30 #define w 4096 /* 8 whitening keys (word) */
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
[all …]
/linux-6.15/Documentation/admin-guide/device-mapper/
Ddm-service-time.rst82 # echo "0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 1 8:16 128 4" \
86 test: 0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 1 8:16 128 4
89 test: 0 10 multipath 2 0 0 0 1 1 E 0 2 2 8:0 A 0 0 1 8:16 A 0 0 4
92 Or '2' for sda and '8' for sdb would be also true::
94 # echo "0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 2 8:16 128 8" \
98 test: 0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 2 8:16 128 8
101 test: 0 10 multipath 2 0 0 0 1 1 E 0 2 2 8:0 A 0 0 2 8:16 A 0 0 8
/linux-6.15/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h147 #define QRXFLXP_CNTXT_RXDID_PRIO_S 8
148 #define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8)
155 #define GLGEN_GPIO_CTL_PIN_FUNC_S 8
156 #define GLGEN_GPIO_CTL_PIN_FUNC_M ICE_M(0xF, 8)
303 #define E800_PRTMAC_HSEC_CTL_TX_PS_QNT_MAX 8
376 #define GLNVM_ULD_POR_DONE_1_M BIT(8)
434 #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8))
435 #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8))
436 #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8))
437 #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8))
[all …]
/linux-6.15/include/linux/clk/
Dat91_pmc.h30 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
62 #define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */
72 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
89 #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
128 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
129 #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
130 #define AT91RM9200_PMC_MDIV_2 (1 << 8)
131 #define AT91RM9200_PMC_MDIV_3 (2 << 8)
132 #define AT91RM9200_PMC_MDIV_4 (3 << 8)
133 #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
[all …]
/linux-6.15/drivers/pinctrl/mediatek/
Dpinctrl-mt8516.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
21 MTK_DRV_GRP(2, 8, 1, 2, 2),
22 /* E8E4E2 2/4/6/8/10/12/14/16 */
36 MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
40 MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
41 MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
42 MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
57 MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
58 MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
[all …]
Dpinctrl-mt8167.c18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
21 MTK_DRV_GRP(2, 8, 1, 2, 2),
22 /* E8E4E2 2/4/6/8/10/12/14/16 */
36 MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
40 MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
41 MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
42 MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
57 MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
58 MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
[all …]
/linux-6.15/drivers/media/platform/renesas/vsp1/
Dvsp1_regs.h22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
23 #define VI6_CLK_DCSWT_CSTPW_SHIFT 8
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
45 #define VI6_DISP_IRQ_ENB_DSTE BIT(8)
50 #define VI6_DISP_IRQ_STA_DST BIT(8)
65 #define VI6_DL_CTRL_DC1 BIT(8)
80 #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8)
81 #define VI6_DL_EXT_CTRL_POLINT_SHIFT 8
125 #define VI6_RPF_INFMT_CSC BIT(8)
133 #define VI6_RPF_DSWAP_A_BTS BIT(8)
[all …]
/linux-6.15/arch/arm/lib/
Dcrc-t10dif-core.S127 * This can be implemented using 8x8 long polynomial multiplication, by
128 * reorganizing the input so that each pairwise 8x8 multiplication
134 * 1 (w0*x1 ^ w1*x0) << 8 ^ | (y0*z1 ^ y1*z0) << 8 ^
141 * 8 w1*x7 << 64 | y1*z7 << 64
148 * and after performing 8x8->16 bit long polynomial multiplication of
164 vext.8 q11, \v64, \v64, #1
166 vuzp.8 q11, \v64
167 vtbl.8 d24, {\v16\()_L-\v16\()_H}, d24
168 vtbl.8 d25, {\v16\()_L-\v16\()_H}, d25
185 vext.8 q12, q12, q12, #14
[all …]

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