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/linux-3.3/arch/x86/include/asm/
Dvmx.h250 #define EXIT_REASON_NMI_WINDOW 8
289 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
300 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
301 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
302 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
303 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
304 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
323 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
326 #define REG_EAX (0 << 8)
327 #define REG_ECX (1 << 8)
[all …]
/linux-3.3/drivers/staging/bcm/
Dcntrl_SignalingInterface.h54 /** 8bit Classifier Rule Priority Of The Service Flow*/
90 /** 8bit Associated PHSI Of The Service Flow*/
108 /** 8bit PHS Index Of The Service Flow*/
118 /** 8bit Total number of bytes to be suppressed for the Service Flow*/
120 …/** 8bit Indicates whether or not Packet Header contents need to be verified prior to supression …
133 /** 8bit Phs Classfier Action Of The Service Flow*/
135 /** 8bit Phs DSC Action Of The Service Flow*/
223 /** 8bit Indicates whether or not MBS service is requested for this Serivce Flow*/
226 …/** 8bit QOS Parameter Set specifies proper application of QoS paramters to Provisioned, Admitted…
229 /** 8bit Traffic Priority Of the Service Flow */
[all …]
/linux-3.3/arch/alpha/lib/
Dmemcpy.c74 n -= 8; /* to avoid compare against 8 in the loop */ in __memcpy_unaligned_up()
80 __asm__("ldq_u %0,%1":"=r" (high_word):"m" (*(unsigned long *)(s+8))); in __memcpy_unaligned_up()
81 n -= 8; in __memcpy_unaligned_up()
88 s += 8; in __memcpy_unaligned_up()
90 d += 8; in __memcpy_unaligned_up()
94 n += 8; in __memcpy_unaligned_up()
120 n -= 8; in __memcpy_aligned_up()
124 n -= 8; in __memcpy_aligned_up()
125 s += 8; in __memcpy_aligned_up()
127 d += 8; in __memcpy_aligned_up()
[all …]
/linux-3.3/arch/powerpc/lib/
Dcopyuser_64.S24 neg r6,r3 /* LS 3 bits = # bytes to 8-byte dest bdry */
29 std r5,-8(r1)
57 220: ld r6,8(r4)
71 270: std r8,8(r3)
73 222: ld r8,8(r4)
79 272: std r8,8(r3)
87 addi r4,r4,8
89 addi r3,r3,8
120 25: ld r0,8(r4)
127 27: ld r0,8(r4)
[all …]
Dmem_64.S17 rlwimi r4,r4,8,16,23
18 andi. r0,r0,7 /* # bytes to be 8-byte aligned */
24 blt cr1,8f
25 beq+ 3f /* if already 8-byte aligned */
41 std r4,8(r6)
53 beq 8f
56 std r4,8(r6)
62 std r4,8(r6)
64 7: bf 31,8f
66 addi r6,r6,8
[all …]
/linux-3.3/include/video/
Dsh_mobile_lcdc.h19 #define LDINTR_VEE (1 << 8)
26 #define LDSR_MRS (1 << 8)
31 #define LDCNT2R_BR (1 << 8)
78 #define LDDFR_YF_420 (0 << 8)
79 #define LDDFR_YF_422 (1 << 8)
80 #define LDDFR_YF_444 (2 << 8)
81 #define LDDFR_YF_MASK (3 << 8)
105 RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
113 SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
114 SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */
[all …]
/linux-3.3/drivers/media/video/davinci/
Dvpbe_osd_regs.h129 #define VPSSBL_INTSTAT_IPIPE_INT1 (1 << 8)
159 #define OSD_MODE_BCLUT (1 << 8)
170 #define OSD_VIDWINMD_ACT1 (1 << 8)
186 #define OSD_OSDWIN0MD_OVZ0_SHIFT 8
187 #define OSD_OSDWIN0MD_OVZ0 (3 << 8)
204 #define OSD_OSDWIN1MD_OVZ1_SHIFT 8
205 #define OSD_OSDWIN1MD_OVZ1 (3 << 8)
217 #define OSD_OSDATRMD_OVZA_SHIFT 8
218 #define OSD_OSDATRMD_OVZA (3 << 8)
224 #define OSD_RECTCUR_RCAD_SHIFT 8
[all …]
/linux-3.3/arch/arm/mach-u300/
Ddummyspichip.c71 * Force chip to 8 bit mode in dummy_looptest()
74 spi->bits_per_word = 8; in dummy_looptest()
78 /* Now run the tests for 8bit mode */ in dummy_looptest()
80 "in 8bit mode\n"); in dummy_looptest()
88 pr_info("Simple test 2: write 8 bytes, read back 8 bytes garbage " in dummy_looptest()
89 "in 8bit mode (full FIFO)\n"); in dummy_looptest()
90 status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8); in dummy_looptest()
98 "in 8bit mode (see if we overflow FIFO)\n"); in dummy_looptest()
106 pr_info("Simple test 4: write 8 bytes with spi_write(), read 8 " in dummy_looptest()
107 "bytes garbage with spi_read() in 8bit mode\n"); in dummy_looptest()
[all …]
/linux-3.3/sound/ppc/
Dawacs.h49 #define MASK_RATE (0x7 << 8) /* Sound Rate */
90 #define MASK_GAINLINE (0x1 << 8) /* Disable Mic preamp */
91 #define MASK_GAINMIC (0x0 << 8) /* Enable Mic preamp */
96 #define SHIFT_GAINLINE 8
114 #define MASK_ADDR1RES2 (0x1 << 8) /* Reserved */
132 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
158 #define MASK_MFGID (0xf << 8) /* Mfg. ID */
161 #define MASK_HDPCONN 8 /* headphone plugged in */
165 #define MASK_LICONN_IMAC 8 /* line-in plugged in */
185 #define RATE_48000 (0x0 << 8) /* 48 kHz */
[all …]
/linux-3.3/drivers/media/dvb/frontends/
Dstv090x_reg.h39 #define STV090x_WIDTH_DACR2_VALUE_FIELD 8
217 #define STV090x_GPIO8CFG STV090x_GPIOxCFG(8)
363 #define STV090x_WIDTH_M_DIV_FIELD 8
457 #define STV090x_WIDTH_FSKTC1_CAR_FIELD 8
461 #define STV090x_WIDTH_FSKTC0_CAR_FIELD 8
469 #define STV090x_WIDTH_FSKTF0_DELTAF_FIELD 8
493 #define STV090x_WIDTH_FSKRC1_CAR_FIELD 8
497 #define STV090x_WIDTH_FSKRC0_CAR_FIELD 8
519 #define STV090x_WIDTH_FSKR_AGC_ACCU_FIELD 8
535 #define STV090x_WIDTH_FSKR_PLL_TRESH0_FIELD 8
[all …]
/linux-3.3/drivers/media/common/
Dsaa7146_hlp.c12 …*clip_format |= (( ((palette&0xf00)>>8) << 30) | ((palette&0x00f) << 24) | (((palette&0x0f0)>>4) … in calculate_output_format_register()
47 {0x00, 2}, {0x02, 4}, {0x00, 4}, {0x06, 8}, {0x02, 8},
48 {0x08, 8}, {0x00, 8}, {0x1E, 16}, {0x0E, 8}, {0x26, 8},
49 {0x06, 8}, {0x42, 8}, {0x02, 8}, {0x80, 8}, {0x00, 8},
50 {0xFE, 16}, {0xFE, 8}, {0x7E, 8}, {0x7E, 8}, {0x3E, 8},
51 {0x3E, 8}, {0x1E, 8}, {0x1E, 8}, {0x0E, 8}, {0x0E, 8},
52 {0x06, 8}, {0x06, 8}, {0x02, 8}, {0x02, 8}, {0x00, 8},
53 {0x00, 8}, {0xFE, 16}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8},
54 {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8},
55 {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8}, {0xFE, 8},
[all …]
/linux-3.3/arch/arm/mach-davinci/
Dda850.c428 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
430 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
431 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
432 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
433 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
434 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
435 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
436 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
437 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
438 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
[all …]
/linux-3.3/include/linux/ssb/
Dssb_regs.h66 #define SSB_IPSFLAG_IRQ2_SHIFT 8
139 #define SSB_IDLOW_MIBL_SHIFT 8
161 #define SSB_IDHIGH_RCHI_SHIFT 8 /* yes, shift 8 is right */
180 #define SSB_SPROM_REVISION_CRC_SHIFT 8
198 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
209 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
213 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
217 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
224 #define SSB_SPROM1_ITSSI_A_SHIFT 8
230 #define SSB_SPROM1_AGAIN_A_SHIFT 8
[all …]
/linux-3.3/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dgio_defs.h101 #define REG_RD_ADDR_gio_rw_pa_oe 8
102 #define REG_WR_ADDR_gio_rw_pa_oe 8
106 unsigned int data : 8;
114 unsigned int oe : 8;
122 unsigned int data : 8;
130 unsigned int oe : 8;
138 unsigned int data : 8;
146 unsigned int oe : 8;
154 unsigned int data : 8;
162 unsigned int oe : 8;
[all …]
Dpio_defs.h91 unsigned int data : 8;
99 unsigned int data : 8;
107 unsigned int data : 8;
110 #define REG_RD_ADDR_pio_rw_io_access2 8
111 #define REG_WR_ADDR_pio_rw_io_access2 8
115 unsigned int data : 8;
123 unsigned int data : 8;
131 unsigned int data : 8;
139 unsigned int data : 8;
147 unsigned int data : 8;
[all …]
/linux-3.3/arch/arm/mach-omap2/
Dcm-regbits-34xx.h60 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
61 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
83 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
84 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
105 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
106 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
128 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8
129 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
158 #define OMAP3430ES1_EN_FAC_MASK (1 << 8)
159 #define OMAP3430ES1_EN_FAC_SHIFT 8
[all …]
Dprm-regbits-34xx.h26 #define OMAP3430_RET_SHIFT 8
27 #define OMAP3430_RET_MASK (0xff << 8)
36 #define OMAP3430_INITVOLTAGE_SHIFT 8
37 #define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
44 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
45 #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
50 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
51 #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
125 #define OMAP3430_MEMRETSTATE_MASK (1 << 8)
137 #define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
[all …]
/linux-3.3/arch/cris/include/arch-v32/arch/hwregs/
Deth_defs.h106 #define REG_RD_ADDR_eth_rw_ma1_lo 8
107 #define REG_WR_ADDR_eth_rw_ma1_lo 8
156 unsigned int dummy1 : 8;
206 unsigned int crc_err : 8;
207 unsigned int align_err : 8;
208 unsigned int oversize : 8;
209 unsigned int congestion : 8;
215 unsigned int crc_err : 8;
216 unsigned int align_err : 8;
217 unsigned int oversize : 8;
[all …]
/linux-3.3/arch/arm/lib/
Dcsumpartialcopygeneric.S30 * we have >= 8 bytes here, so we don't need to check
92 cmp len, #8 @ Ensure that we have at least
93 blo .Lless8 @ 8 bytes to copy.
125 tst ip, #8
163 movne r0, r0, ror #8
174 mov r4, r5, pull #8 @ C = 0
179 mov r5, r5, pull #8
181 mov r6, r6, pull #8
183 mov r7, r7, pull #8
190 mov r4, r8, pull #8
[all …]
/linux-3.3/arch/blackfin/mach-bf561/include/mach/
Dirq.h24 #define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
38 #define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
57 #define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
69 #define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
73 #define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
74 #define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
75 #define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
76 #define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
77 #define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
78 #define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
[all …]
/linux-3.3/arch/sh/lib64/
Dmemcpy.S66 .balign 8
74 .balign 8
92 L8_15: /* 8..15 byte memcpy cntd. */
96 stlo.q r5, -8, r6
118 /* 8 .. 15 byte memcpy */
121 ldlo.q r6, -8, r7
129 LDUAQ (r3, 8, r8, r9)
134 ldlo.q r6, -8, r7
136 stlo.q r2, 8, r8
140 stlo.q r5, -8, r6
[all …]
Dstrcpy.S28 addi r2, 8, r0
33 ori r3,-8,r23
36 addi r21, 8, r20
39 ori r2,-8,r22
54 addi r0, 8, r0
65 addi r0, 8, r0
72 st.b r0,-8,r4
74 shlri r4,8,r4
79 .balign 8
88 stlo.q r0, -8, r4
[all …]
/linux-3.3/arch/ia64/lib/
Dxor.S43 (p[0]) ld8.nta s1[0] = [r16], 8
44 (p[0]) ld8.nta s2[0] = [r17], 8
46 (p[6+1])st8.nta [r8] = d[1], 8
81 (p[0]) ld8.nta s1[0] = [r16], 8
82 (p[0]) ld8.nta s2[0] = [r17], 8
85 (p[0]) ld8.nta s3[0] = [r18], 8
86 (p[6+1])st8.nta [r8] = d[1], 8
122 (p[0]) ld8.nta s1[0] = [r16], 8
123 (p[0]) ld8.nta s2[0] = [r17], 8
125 (p[0]) ld8.nta s3[0] = [r18], 8
[all …]
/linux-3.3/arch/openrisc/lib/
Dstring.S40 l.sw 8(r1),r3
46 8: l.lbz r6,0(r4)
56 l.lwz r3,8(r1)
67 .long 8b, 99b // read fault
78 l.addi r1,r1,-8
95 l.addi r1,r1,8
117 l.sw 8(r1),r4
124 8: l.lbz r6,0(r4)
138 l.lwz r4,8(r1)
150 l.lwz r4,8(r1)
[all …]
/linux-3.3/arch/mips/include/asm/octeon/
Dcvmx-pcieep-defs.h213 uint32_t reserved_11_18:8;
235 uint32_t bcc:8;
236 uint32_t sc:8;
237 uint32_t pi:8;
238 uint32_t rid:8;
249 uint32_t bist:8;
252 uint32_t lt:8;
253 uint32_t cls:8;
460 uint32_t cp:8;
471 uint32_t ml:8;
[all …]

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