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/linux-3.3/arch/arm/include/asm/
Dvfp.h40 #define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
41 #define FPEXC_IDF (1 << 7)
61 #define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
73 #define FPSCR_IDC (1<<7)
/linux-3.3/sound/spi/
Dat73c213.h30 #define DAC_CTRL_ONPADRV 7
65 #define DAC_OLC_RSHORT 7
85 #define DAC_MISC_VCMCAPSEL 7
93 #define DAC_PRECH_PRCHGPDRV 7
/linux-3.3/drivers/mmc/host/
Dpxamci.h10 #define STAT_RECV_FIFO_FULL (1 << 7)
30 #define CMDAT_DMAEN (1 << 7)
41 #define MMC_RESTO 0x0014 /* 7 bit */
60 #define TINT (1 << 7)
/linux-3.3/drivers/net/wireless/wl12xx/
Drx.h35 #define PBCC_RATE_BIT BIT(7)
41 #define NUM_RX_PKT_DESC_MOD_MASK 7
64 * Bits 5-7 - encryption
87 * Bits 6-7 - reserved
/linux-3.3/drivers/video/
Dvt8623fb.c64 static const struct svga_pll vt8623_pll = {2, 127, 2, 7, 0, 3,
69 static struct vga_regset vt8623_h_total_regs[] = {{0x00, 0, 7}, {0x36, 3, 3}, VGA_REGSET_END};
70 static struct vga_regset vt8623_h_display_regs[] = {{0x01, 0, 7}, VGA_REGSET_END};
71 static struct vga_regset vt8623_h_blank_start_regs[] = {{0x02, 0, 7}, VGA_REGSET_END};
72 static struct vga_regset vt8623_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, {0x33, 5, 5}, V…
73 static struct vga_regset vt8623_h_sync_start_regs[] = {{0x04, 0, 7}, {0x33, 4, 4}, VGA_REGSET_END};
76 static struct vga_regset vt8623_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {…
77 static struct vga_regset vt8623_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {…
78 static struct vga_regset vt8623_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {…
79 static struct vga_regset vt8623_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
[all …]
/linux-3.3/arch/arm/mach-mxs/include/mach/
Diomux-mx23.h33 #define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0)
66 #define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0)
98 #define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0)
131 #define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0)
155 #define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1)
180 #define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1)
204 #define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1)
215 #define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2)
253 #define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2)
264 #define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
[all …]
/linux-3.3/drivers/media/video/
Dtda7432.c128 /* Lower 7 bits control volume from -79dB to +32dB in 1dB steps
136 * MSB (bit 7) controls loudness: 1/0 is loudness on/off
140 #define TDA7432_LD_ON 1 << 7
156 * Bit 7 controls bass attenuation/gain (sign)
157 * 1 << 7 = gain (+)
158 * 0 << 7 = attenuation (-)
165 #define TDA7432_TREBLE 7
168 #define TDA7432_BASS 7 << 4
169 #define TDA7432_BASS_GAIN 1 << 7
185 * Bits 6,7 unused
[all …]
/linux-3.3/drivers/staging/panel/
Dlcd-panel-cgram.txt2 characters 0 to 7. The escape code to define a new character is
3 '\e[LG' followed by one digit from 0 to 7, representing the character
8 bits of the 7 first bytes are used for each character. If the string
/linux-3.3/arch/alpha/include/asm/
Dirqflags.h14 #define IPL_MCHECK 7
15 #define IPL_MAX 7
23 #define getipl() (rdps() & 7)
/linux-3.3/include/linux/
Dlis3lv02d.h73 #define LIS3_IRQ1_CLICK (7 << 0)
74 #define LIS3_IRQ1_MASK (7 << 0)
80 #define LIS3_IRQ2_CLICK (7 << 3)
81 #define LIS3_IRQ2_MASK (7 << 3)
83 #define LIS3_IRQ_ACTIVE_LOW (1 << 7)
/linux-3.3/arch/arm/mach-ks8695/include/mach/
Dregs-mem.h40 #define EXTACON_EBTACT (7 << 9) /* Write Enable/Output Enable Active Time */
41 #define EXTACON_EBTCOH (7 << 6) /* Chip Select Hold Time */
42 #define EXTACON_EBTACS (7 << 3) /* Address Setup Time before ECSN */
43 #define EXTACON_EBTCOS (7 << 0) /* Chip Select Time before OEN */
48 #define ROMCON_RBTACC (7 << 4) /* Access Cycle Time */
/linux-3.3/arch/s390/oprofile/
Dhwsampler.h17 unsigned int b15_21:7; /* 15-21: zeros */
19 unsigned int b23_29:7; /* 23-29: zeros */
23 unsigned int:16; /* 6-7: reserved */
35 { /* bytes 0 - 7 Bit(s) */
40 unsigned int b55_61:7; /* 55-61: - zeros */
/linux-3.3/sound/oss/
Dulaw.h2 3, 7, 11, 15, 19, 23, 27, 31,
40 5, 6, 6, 6, 6, 7, 7, 7,
41 7, 8, 8, 8, 8, 9, 9, 9,
/linux-3.3/arch/arm/mach-at91/include/mach/
Dgsia18s.h16 #define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
25 #define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
33 /* bit 7 not used */
/linux-3.3/Documentation/scsi/
Darcmsr_spec.txt63 ** 7. Definition of SGL entry (structure)
103 ** byte 7 : second (0..59)
224 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a
242 ** byte 7/8 : Fan#0 (RPM)
259 ** byte 7 : raid level
418 ** byte 4 : 0/1/2/3/4/5/6/7
421 ** (0:7 bit, 1:8 bit : must be 8 bit)
423 ** byte 7 : parity (0:none, 1:off, 2:even)
433 ** byte 4/5/6/7 : IP address
440 ** byte 6 : scsi lun (0-->7)
[all …]
/linux-3.3/sound/soc/codecs/
Dwm8974.c111 SOC_SINGLE("High Pass Cut Off", WM8974_ADC, 4, 7, 0),
124 SOC_ENUM("Equaliser EQ3 Bandwith", wm8974_enum[7]),
140 SOC_SINGLE("DAC Playback Limiter Threshold", WM8974_DACLIM2, 4, 7, 0),
144 SOC_SINGLE("ALC Capture Max Gain", WM8974_ALC1, 3, 7, 0),
145 SOC_SINGLE("ALC Capture Min Gain", WM8974_ALC1, 0, 7, 0),
148 SOC_SINGLE("ALC Capture Hold", WM8974_ALC2, 4, 7, 0),
156 SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8974_NGATE, 0, 7, 0),
158 SOC_SINGLE("Capture PGA ZC Switch", WM8974_INPPGA, 7, 1, 0),
161 SOC_SINGLE("Speaker Playback ZC Switch", WM8974_SPKVOL, 7, 1, 0),
203 SOC_DAPM_SINGLE("Aux Volume", WM8974_ADCBOOST, 0, 7, 0);
[all …]
/linux-3.3/drivers/scsi/
Dqlogicfas408.c66 static int qlcfg8 = (SLOWCABLE << 7) | (QL_ENABLE_PARITY << 4);
124 rtrc(7) in ql_pdma()
160 rtrc(7) in ql_pdma()
227 else if (inb(qbase + 7) & 0x1f) in ql_icmd()
241 outb(qlcfg7, qbase + 7); in ql_icmd()
244 outb(qlcfg9 & 7, qbase + 9); /* prescaler */ in ql_icmd()
285 j &= 7; /* j = inb( qbase + 7 ) >> 5; */ in ql_pcmd()
294 j, i, inb(qbase + 7) & 0x1f); in ql_pcmd()
299 if (inb(qbase + 7) & 0x1f) /* if some bytes in fifo */ in ql_pcmd()
361 j = inb(qbase + 7) & 0x1f; /* and bytes rec'd */ in ql_pcmd()
[all …]
/linux-3.3/drivers/power/
Dds2780_battery.c176 * Sign bit of the voltage value is in bit 7 of the voltage MSB register in ds2780_get_voltage()
179 * Bits 2 - 0 of the voltage value are in bits 7 - 5 of the in ds2780_get_voltage()
204 * Sign bit of the temperature value is in bit 7 of the temperature in ds2780_get_temperature()
208 * Bits 2 - 0 of the temperature value are in bits 7 - 5 of the in ds2780_get_temperature()
257 * Sign bit of the current value is in bit 7 of the current MSB register in ds2780_get_current()
260 * Bits 7 - 0 of the current value are in bits 7 - 0 of the current in ds2780_get_current()
295 * Bits 15 - 8 of the ACR value are in bits 7 - 0 of the ACR in ds2780_get_accumulated_current()
297 * Bits 7 - 0 of the ACR value are in bits 7 - 0 of the ACR in ds2780_get_accumulated_current()
355 * Bits 15 - 8 of the RAAC value are in bits 7 - 0 of the RAAC in ds2780_get_charge_now()
357 * Bits 7 - 0 of the RAAC value are in bits 7 - 0 of the RAAC in ds2780_get_charge_now()
/linux-3.3/drivers/net/phy/
Ddp83640_reg.h60 #define TRIG_READ (1<<7) /* Read PTP Trigger */
80 #define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
81 #define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
88 #define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
115 #define E7_RISE (1<<15) /* Indicates direction of Event 7 */
116 #define E7_DET (1<<14) /* Indicates Event 7 detected */
123 #define E3_RISE (1<<7) /* Indicates direction of Event 3 */
139 #define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
162 #define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
180 #define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
[all …]
/linux-3.3/arch/arm/mach-omap2/
Dprm-regbits-34xx.h71 #define OMAP3430_EN_PER_SHIFT 7
72 #define OMAP3430_EN_PER_MASK (1 << 7)
138 #define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
149 #define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
239 #define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
240 #define OMAP3430_MPU_DPLL_ST_SHIFT 7
271 #define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
272 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
389 #define OMAP3430_CLKOUT_EN_MASK (1 << 7)
390 #define OMAP3430_CLKOUT_EN_SHIFT 7
[all …]
/linux-3.3/arch/blackfin/include/mach-common/
Dirq.h23 * Peripherals IVG7 7
43 #define BFIN_IRQ(x) ((x) + 7)
45 #define IVG7 7
/linux-3.3/arch/mips/include/asm/netlogic/xlp-hal/
Dpic.h102 #define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103 #define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104 #define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105 #define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106 #define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107 #define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108 #define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
167 #define PIC_IRT_TIMER_3_INDEX 7
244 #define PIC_CLOCK_TIMER 7
/linux-3.3/include/drm/
Ddrm_fourcc.h35 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
38 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
39 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
100 * index 0 = Y plane, [7:0] Y
116 * index 0: Y plane, [7:0] Y
117 * index 1: Cb plane, [7:0] Cb
118 * index 2: Cr plane, [7:0] Cr
120 * index 1: Cr plane, [7:0] Cr
121 * index 2: Cb plane, [7:0] Cb
/linux-3.3/drivers/net/ethernet/i825xx/
D3c523.h204 unsigned char adr_len; /* adr_len(0-2),al_loc(3),pream(4-5),loopbak(6-7)*/
205 unsigned char priority; /* lin_prio(0-2),exp_prio(4-6),bof_metd(7) */
208 unsigned char time_high; /* slot time high(0-2) and max. retries(4-7) */
209 unsigned char promisc; /* promisc-mode(0) , et al (1-7) */
210 unsigned char carr_coll; /* carrier(0-3)/collision(4-7) stuff */
296 7,6: (read-only) shows selected irq
298 01 = 7
305 1: int 7
318 #define ELMC_REVISION 7 /* revision register, first 4 bits only */
/linux-3.3/drivers/net/wireless/zd1211rw/
Dzd_rf_rf2959.c34 RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
76 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
87 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
95 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
101 case 7:
106 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
110 bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
118 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
136 bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),

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