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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-minipack.dts206 * to PIM (Port Interface Module) #7 (1-based).
218 * I2C Switch 47-0073 (channel #7 of 11-0070): connecting
396 imux23: i2c@7 {
399 reg = <7>;
493 imux55: i2c@7 {
496 reg = <7>;
559 imux63: i2c@7 {
562 reg = <7>;
625 imux71: i2c@7 {
628 reg = <7>;
[all …]
/linux/Documentation/devicetree/bindings/edac/
H A Dapm-xgene-edac.txt51 csw: csw@7e200000 {
56 mcba: mcba@7e700000 {
61 mcbb: mcbb@7e720000 {
71 rb: rb@7e000000 {
91 edacmc@7e800000 {
97 edacpmd@7c000000 {
103 edacl3@7e600000 {
108 edacsoc@7e930000 {
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h79 uint32_t MmHubPadding[7]; // SMU internal use
87 #define VG_NUM_DCFCLK_DPM_LEVELS 7
88 #define VG_NUM_DISPCLK_DPM_LEVELS 7
89 #define VG_NUM_DPPCLK_DPM_LEVELS 7
90 #define VG_NUM_SOCCLK_DPM_LEVELS 7
91 #define VG_NUM_ISPICLK_DPM_LEVELS 7
92 #define VG_NUM_ISPXCLK_DPM_LEVELS 7
133 uint32_t MmHubPadding[7]; // SMU internal use
/linux/include/dt-bindings/clock/
H A Dexynos7-clk.h17 #define DOUT_ACLK_MSCL_532 7
41 #define CLK_SCLK_SPI0 7
60 #define CLK_SCLK_MMC1 7
84 #define PCLK_HSI2C9 7
99 #define PCLK_HSI2C2 7
137 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
150 #define SCLK_UFSUNIPRO20_USER 7
168 #define ACLK_LH_ASYNC_SI_MSCL_0 7
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32f769.c72 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
109 PINCTRL_PIN(7, "PA7"),
168 STM32_FUNCTION(7, "UART4_RX"),
181 STM32_FUNCTION(7, "UART4_TX"),
211 STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
225 STM32_FUNCTION(7, "DFSDM_CKOUT"),
240 STM32_FUNCTION(7, "DFSDM_DATIN1"),
251 STM32_FUNCTION(7, "SAI1_SD_A"),
264 STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
278 STM32_FUNCTION(7, "SPI3_MISO"),
[all …]
/linux/drivers/crypto/hisilicon/sec2/
H A Dsec_crypto.h154 * flag: 7-10 bits
175 * auth: 6~7 bit s
183 * src_addr_type: ~7 bit, with sdm_addr_type 0-1 bits
191 * mac_addr_type: 5~7 bits
200 * ci_gen: 6~7 bits
215 * write_frame_len(type2): 5~7 bits
222 * inveld: 7 bit
265 * reserved: 5~7 bits
315 * c_alg : 4~7 bits
324 * reserved : 7 bits
[all …]
/linux/include/linux/mfd/
H A Das3722.h175 #define AS3722_LDO_ILIMIT_MASK BIT(7)
176 #define AS3722_LDO_ILIMIT_BIT BIT(7)
200 #define AS3722_LDO7_CTRL BIT(7)
238 #define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7)
247 #define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7)
256 #define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7)
265 #define AS3722_INTERRUPT_MASK4_ADC BIT(7)
272 #define AS3722_ADC1_INT_MASK BIT(7)
277 #define AS3722_ADC0_CONV_START BIT(7)
278 #define AS3722_ADC0_CONV_NOTREADY BIT(7)
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v7_2.c62 case IP_VERSION(7, 2, 1): in nbio_v7_2_get_rev_id()
63 case IP_VERSION(7, 3, 0): in nbio_v7_2_get_rev_id()
64 case IP_VERSION(7, 5, 0): in nbio_v7_2_get_rev_id()
81 case IP_VERSION(7, 2, 1): in nbio_v7_2_mc_access_enable()
82 case IP_VERSION(7, 3, 0): in nbio_v7_2_mc_access_enable()
83 case IP_VERSION(7, 5, 0): in nbio_v7_2_mc_access_enable()
265 case IP_VERSION(7, 2, 1): in nbio_v7_2_update_medium_grain_light_sleep()
266 case IP_VERSION(7, 3, 0): in nbio_v7_2_update_medium_grain_light_sleep()
267 case IP_VERSION(7, 5, 0): in nbio_v7_2_update_medium_grain_light_sleep()
372 case IP_VERSION(7, 2, 1): in nbio_v7_2_init_registers()
[all …]
/linux/drivers/media/platform/amlogic/meson-ge2d/
H A Dge2d-regs.h48 #define GE2D_SRC1_GB_ALPHA GENMASK(7, 0)
68 #define GE2D_SRC1_LITTLE_ENDIAN BIT(7)
92 #define GE2D_COLOR_MAP_ARGB1555 7
93 #define GE2D_COLOR_MAP_AYUV1555 7
125 #define GE2D_DST_XY_SWAP BIT(7)
137 #define GE2D_DP_STATUS GENMASK(16, 7)
156 #define GE2D_RD_SRC1_STATE_CR GENMASK(7, 6)
167 #define GE2D_COLOR_ALPHA GENMASK(7, 0)
188 #define GE2D_LUT_ADDR GENMASK(7, 0)
205 #define GE2D_DST1_CANVAS_ADDR GENMASK(7, 0)
[all …]
/linux/drivers/net/ethernet/netronome/nfp/flower/
H A Dcmsg.h24 #define NFP_FLOWER_LAYER_VXLAN BIT(7)
30 #define NFP_FLOWER_LAYER2_TUN_IPV6 BIT(7)
41 #define NFP_FL_IP_FRAG_FIRST BIT(7)
77 #define NFP_FL_ACTION_OPCODE_SET_ETHERNET 7
104 #define NFP_FL_TUNNEL_TYPE GENMASK(7, 4)
271 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
288 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
300 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
311 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
330 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h23 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
47 #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7)
110 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
140 #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
157 #define MT_US_CYC_CNT GENMASK(7, 0)
191 #define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
264 #define MT_BBP_CSR_CFG_VAL GENMASK(7, 0)
290 #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
297 #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
338 #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
[all …]
/linux/crypto/
H A Drmd160.c70 ROUND(ee, aa, bb, cc, dd, F1, K1, in[6], 7); in rmd160_transform()
71 ROUND(dd, ee, aa, bb, cc, F1, K1, in[7], 9); in rmd160_transform()
77 ROUND(cc, dd, ee, aa, bb, F1, K1, in[13], 7); in rmd160_transform()
82 ROUND(ee, aa, bb, cc, dd, F2, K2, in[7], 7); in rmd160_transform()
88 ROUND(dd, ee, aa, bb, cc, F2, K2, in[15], 7); in rmd160_transform()
90 ROUND(bb, cc, dd, ee, aa, F2, K2, in[12], 7); in rmd160_transform()
95 ROUND(bb, cc, dd, ee, aa, F2, K2, in[14], 7); in rmd160_transform()
103 ROUND(aa, bb, cc, dd, ee, F3, K3, in[4], 7); in rmd160_transform()
109 ROUND(ee, aa, bb, cc, dd, F3, K3, in[7], 8); in rmd160_transform()
114 ROUND(ee, aa, bb, cc, dd, F3, K3, in[5], 7); in rmd160_transform()
[all …]
/linux/include/dt-bindings/interconnect/
H A Dqcom,sm8250.h18 #define MASTER_UFS_MEM 7
32 #define MASTER_PCIE_1 7
50 #define SLAVE_CAMERA_CFG 7
107 #define MASTER_MNOC_SF_MEM_NOC 7
128 #define MASTER_MDP_PORT0 7
142 #define SLAVE_NPU_DPM 7
156 #define SLAVE_APPSS 7
H A Dqcom,sc7280.h18 #define MASTER_SDCC_2 7
34 #define SLAVE_SERVICE_A2NOC 7
48 #define SLAVE_RBCPR_CX_CFG 7
96 #define SLAVE_DDRSS_CFG 7
116 #define MASTER_MNOC_SF_MEM_NOC 7
147 #define SLAVE_MNOC_HF_MEM_NOC 7
163 #define SLAVE_SERVICE_SNOC 7
H A Dqcom,sm8450.h17 #define SLAVE_SERVICE_A1NOC 7
26 #define MASTER_SP 7
47 #define SLAVE_CDSP_CFG 7
103 #define MASTER_COMPUTE_NOC 7
122 #define SLAVE_SERVICES_LPASS_AML_NOC 7
137 #define MASTER_VIDEO 7
167 #define SLAVE_SNOC_GEM_NOC_GC 7
/linux/include/drm/display/
H A Ddrm_dp.h62 #define DP_MSA_MISC_RAW_16_BPC (7 << 5)
119 # define DP_ENHANCED_FRAME_CAP (1 << 7)
125 # define DP_TPS4_SUPPORTED (1 << 7)
146 # define DP_OUI_SUPPORT (1 << 7)
173 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
207 # define DP_AG_FACTOR_1US (7 << 0)
270 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
293 # define DP_DSC_MAX_BPP_DELTA_AVAILABILITY (1 << 7) /* eDP 1.5 & DP 2.0 */
317 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
335 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dpwrseq.h52 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
55 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \
76 /*0x1F[7:0] = 0 turn off RF*/}, \
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7) \
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
166 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
171 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
223 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0 \
224 /*Polling 0x109[7]=0 TSF in 40M*/}, \
226 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0 \
[all …]
/linux/drivers/clk/rockchip/
H A Dclk-rv1108.c88 RV1108_CPUCLK_RATE(1608000000, 7),
89 RV1108_CPUCLK_RATE(1512000000, 7),
189 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
286 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
289 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
320 RV1108_CLKGATE_CON(7), 9, GFLAGS),
324 RV1108_CLKGATE_CON(17), 7, GFLAGS),
327 RV1108_CLKGATE_CON(7), 10, GFLAGS),
334 RV1108_CLKGATE_CON(7), 11, GFLAGS),
341 RV1108_CLKGATE_CON(7), 12, GFLAGS),
[all …]
/linux/Documentation/RCU/Design/Expedited-Grace-Periods/
H A DExpRCUFlow.svg47 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
74 id="path3852-7"
84 id="Arrow2Lend-7"
90 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
104 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
118 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
132 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
146 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
160 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
174 …72895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z"
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Dhive_isp_css_defs.h65 #define HIVE_GP_REGS_MOD_STREAM_STAT_IDX 7
88 #define HIVE_GP_REGS_SRST_FACELLFIFOS 7
126 #define HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID 7
162 #define HIVE_GP_DEV_TC_GPIO_PIN_7_BIT_ID 7
188 #define HIVE_GP_TIMER_7 7
202 #define HIVE_GP_TIMER_GPIO_7_BIT_ID 7
264 #define SP_STR_MON_PORT_ISP2SP 7
309 #define ISP_STR_MON_PORT_GDC12ISP 7
340 #define MOD_STR_MON_PORT_SP2MC 7
357 #define MOD_STR_MON_PORT_RCV_MC 7
[all …]
/linux/drivers/usb/typec/tcpm/
H A Dfusb302_reg.h13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
22 #define FUSB_REG_SWITCHES1_POWERROLE BIT(7)
30 #define FUSB_REG_MEASURE_MDAC5 BIT(7)
73 #define FUSB_REG_MASK_VBUSOK BIT(7)
91 #define FUSB_REG_MASKA_OCP_TEMP BIT(7)
121 #define FUSB_REG_INTERRUPTA_OCP_TEMP BIT(7)
132 #define FUSB_REG_STATUS0_VBUSOK BIT(7)
146 #define FUSB_REG_STATUS1_RXSOP2 BIT(7)
153 #define FUSB_REG_INTERRUPT_VBUSOK BIT(7)
/linux/arch/arm/boot/dts/nspire/
H A Dnspire-cx.dts54 MATRIX_KEY(0, 7, 0x0b)
63 MATRIX_KEY(1, 7, 0x02)
72 MATRIX_KEY(2, 7, 0x05)
82 MATRIX_KEY(3, 7, 0x08)
91 MATRIX_KEY(4, 7, 0x0d)
109 MATRIX_KEY(6, 7, 0x01)
111 MATRIX_KEY(7, 8, 0x2a)
112 MATRIX_KEY(7, 9, 0x1d)
113 MATRIX_KEY(7, 10, 0x33)
/linux/arch/mips/include/asm/sn/sn0/
H A Dhubmd.h116 #define MD_SIZE_512MB 7 /* Valid in MEMORY_CONFIG */
149 #define MMC_BANK_MASK(_b) (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
210 #define MSU_CORECLK_TST_SHFT 7 /* You don't wanna know */
211 #define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
212 #define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
227 #define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
228 #define MSU_SN00_SLOTID_SHFT 7
264 #define MD_BANK_MASK (UINT64_CAST 7 << 29)
308 #define MD_PDIR_AX_SHFT 7 /* ABC low */
309 #define MD_PDIR_AX_MASK (1 << 7)
[all …]
/linux/arch/x86/include/asm/
H A Dcpufeatures.h28 #define X86_FEATURE_MCE ( 0*32+ 7) /* "mce" Machine Check Exception */
79 /* Free ( 3*32+ 7) */
113 #define X86_FEATURE_EST ( 4*32+ 7) /* "est" Enhanced SpeedStep */
142 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
158 #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* "misalignsse" Misaligned SSE mode */
180 * CPUID levels like 0x6, 0xA etc, word 7.
184 #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* "ring3mwait" Ring 3 MONITOR/MWAIT instructions */
185 #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* "cpuid_fault" Intel CPUID faulting */
186 #define X86_FEATURE_CPB ( 7*32+ 2) /* "cpb" AMD Core Performance Boost */
187 #define X86_FEATURE_EPB ( 7*32+ 3) /* "epb" IA32_ENERGY_PERF_BIAS support */
[all …]
/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h28 #define X86_FEATURE_MCE ( 0*32+ 7) /* "mce" Machine Check Exception */
79 /* Free ( 3*32+ 7) */
113 #define X86_FEATURE_EST ( 4*32+ 7) /* "est" Enhanced SpeedStep */
142 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
158 #define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* "misalignsse" Misaligned SSE mode */
180 * CPUID levels like 0x6, 0xA etc, word 7.
184 #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* "ring3mwait" Ring 3 MONITOR/MWAIT instructions */
185 #define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* "cpuid_fault" Intel CPUID faulting */
186 #define X86_FEATURE_CPB ( 7*32+ 2) /* "cpb" AMD Core Performance Boost */
187 #define X86_FEATURE_EPB ( 7*32+ 3) /* "epb" IA32_ENERGY_PERF_BIAS support */
[all …]

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