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/linux/arch/powerpc/crypto/
H A Daes-tab-4k.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * instructions. E.g. evldw, evlwwsplat, ...
16 * For the safety-conscious it has to be noted that they might be vulnerable
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
32 /* encryption table, same as crypto_ft_tab in crypto/aes-generic.c */
33 .long R(c6, 63, 63, a5), R(f8, 7c, 7c, 84)
34 .long R(ee, 77, 77, 99), R(f6, 7b, 7b, 8d)
35 .long R(ff, f2, f2, 0d), R(d6, 6b, 6b, bd)
36 .long R(de, 6f, 6f, b1), R(91, c5, c5, 54)
38 .long R(ce, 67, 67, a9), R(56, 2b, 2b, 7d)
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/linux/arch/m68k/fpsp040/
H A Dtbldo.S10 | index with a 10-bit index, with the first
11 | 7 bits the opcode, and the remaining 3
46 | instruction ;opcode-stag Notes
49 .long smovcr |$00-0 fmovecr all
50 .long smovcr |$00-1 fmovecr all
51 .long smovcr |$00-2 fmovecr all
52 .long smovcr |$00-3 fmovecr all
53 .long smovcr |$00-4 fmovecr all
54 .long smovcr |$00-5 fmovecr all
55 .long smovcr |$00-6 fmovecr all
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/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
23 - e GRBG 0
24 - e RGGB 1
25 - e BGGR 2
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/linux/arch/mips/include/asm/
H A Dpgtable-32.h19 #include <asm-generic/pgtable-nopmd.h>
26 * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
28 * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
29 * our 2-level table layout would normally have a PGD entry cover a contiguous
30 * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
37 * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
39 * NOTE: We don't yet support huge pages if extended-addressing is enabled
40 * (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
46 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
56 * Basically we have the same two-level (which is the logical three level
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/linux/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-csum_ipv6_magic.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17 * E - either cluster
18 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32 * Then turn it back into a sign extended 32-bit item
35 * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36 * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
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H A Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
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/linux/Documentation/gpu/amdgpu/display/
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/linux/Documentation/networking/device_drivers/can/ctu/
H A Dfsm_txt_buffer_user.svg1 <?xml version="1.0" encoding="UTF-8"?>
2 …mlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#">
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26 …6) rotate(180) translate(0)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
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/linux/lib/crypto/x86/
H A Dsha256-avx-asm.S2 # Implement fast SHA-256 with AVX1 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
40 # This code is described in an Intel White-Paper:
41 # "Fast SHA-256 Implementations on Intel Architecture Processors"
58 # Add reg to mem using reg-mem add and store
66 shld $(32-(\p1)), \p2, \p2
93 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
94 SHUF_DC00 = %xmm12 # shuffle xDxC -> DC00
104 e = %edx define
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H A Dsha256-ssse3-asm.S2 # Implement fast SHA-256 with SSSE3 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
57 # Add reg to mem using reg-mem add and store
86 SHUF_00BA = %xmm10 # shuffle xBxA -> 00BA
87 SHUF_DC00 = %xmm11 # shuffle xDxC -> DC00
97 e = %edx define
139 f = e
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H A Dsha256-avx2-asm.S2 # Implement fast SHA-256 with AVX2 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
59 # Add reg to mem using reg-mem add and store
86 SHUF_00BA = %ymm10 # shuffle xBxA -> 00BA
87 SHUF_DC00 = %ymm12 # shuffle xDxC -> DC00
97 e = %edx # clobbers NUM_BLKS define
145 f = e
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/linux/Documentation/i2c/
H A Di2c_bus.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
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/linux/arch/x86/include/asm/
H A Dpgtable-3level.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Intel Physical Address Extension (PAE) Mode - three-level page
12 #define pte_ERROR(e) \ argument
14 __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
15 #define pmd_ERROR(e) \ argument
17 __FILE__, __LINE__, &(e), pmd_val(e))
18 #define pgd_ERROR(e) \ argument
20 __FILE__, __LINE__, &(e), pgd_val(e))
34 * value and then use set_pte to update it. -ben
38 WRITE_ONCE(ptep->pte_high, pte.pte_high); in native_set_pte()
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/linux/Documentation/ABI/stable/
H A Dsysfs-class-tpm4 Contact: linux-integrity@vger.kernel.org
12 Contact: linux-integrity@vger.kernel.org
24 Contact: linux-integrity@vger.kernel.org
32 Contact: linux-integrity@vger.kernel.org
49 Contact: linux-integrity@vger.kernel.org
50 Description: The "durations" property shows the 3 vendor-specific values
72 Contact: linux-integrity@vger.kernel.org
81 Contact: linux-integrity@vger.kernel.org
89 Contact: linux-integrity@vger.kernel.org
97 PCR-00: 3A 3F 78 0F 11 A4 B4 99 69 FC AA 80 CD 6E 39 57 C3 3B 22 75
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp15-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
9 /omit-if-no-ref/
10 adc1_ain_pins_a: adc1-ain-0 {
21 /omit-if-no-ref/
22 adc1_in6_pins_a: adc1-in6-0 {
28 /omit-if-no-ref/
29 adc1_in10_pins_a: adc1-in10-0 {
35 /omit-if-no-ref/
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/linux/lib/tests/
H A Dcmdline_kunit.c1 // SPDX-License-Identifier: GPL-2.0+
12 "\"\"", "" , "=" , "\"-", "," , "-," , ",-" , "-" ,
13 "+," , "--", ",,", "''" , "\"\",", "\",\"", "-\"\"", "\"",
24 "-7" , "--7" , "-1-2" , "7--9",
25 "7-" , "-7--9", "7-9," , "9-7" ,
26 "5-a", "a-5" , "5-8" , ",8-5",
27 "+,1", "-,4" , "-3,0-1,6", "4,-" ,
28 " +2", " -9" , "0-1,-3,6", "- 9" ,
32 { 1, -7, }, { 0, -0, }, { 4, -1, 0, +1, 2, }, { 0, 7, },
33 { 0, +7, }, { 0, -7, }, { 3, +7, 8, +9, 0, }, { 0, 9, },
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/linux/tools/perf/arch/x86/tests/
H A Dinsn-x86-dat-64.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk
4 * from insn-x86-dat-src.c for inclusion by insn-x86.c
11 "c4 e2 7d 13 eb \tvcvtph2ps %xmm3,%ymm5",},
24 {{0x0f, 0x90, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
26 {{0x0f, 0x91, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
28 {{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
30 {{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
32 {{0x0f, 0x92, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
34 {{0x0f, 0x93, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
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/linux/net/netfilter/
H A Dnft_set_pipapo_avx2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2019-2020 Red Hat GmbH
29 /* Load from memory into YMM register with non-temporal hint ("stream load"),
33 * - loading buckets from lookup tables, as they are not going to be used
36 * - loading the result bitmap from the previous field, as it's never used
75 * nft_pipapo_avx2_prepare() - Prepare before main algorithm body
86 * nft_pipapo_avx2_fill() - Fill a bitmap region with ones
91 * This is nothing else than a version of bitmap_set(), as used e.g. by
113 *data |= GENMASK(len - 1 + offset, offset); in nft_pipapo_avx2_fill()
118 len -= BITS_PER_LONG - offset; in nft_pipapo_avx2_fill()
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/linux/Documentation/RCU/Design/Memory-Ordering/
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/linux/tools/perf/pmu-events/arch/x86/
H A Dmapfile.csv1 Family-model,Version,Filename,EventType
2 GenuineIntel-6-(97|9A|B7|BA|BF),v1.31,alderlake,core
3 GenuineIntel-6-BE,v1.31,alderlaken,core
4 GenuineIntel-6-C[56],v1.09,arrowlake,core
5 GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
6 GenuineIntel-6-(3D|47),v30,broadwell,core
7 GenuineIntel-6-56,v12,broadwellde,core
8 GenuineIntel-6-4F,v23,broadwellx,core
9 GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
10 GenuineIntel-6-DD,v1.00,clearwaterforest,core
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/linux/sound/core/
H A Dpcm_drm_eld.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #define SAD0_CHANNELS_MASK GENMASK(2, 0) /* max number of channels - 1 */
16 #define SAD0_FORMAT_MASK GENMASK(6, 3) /* audio format */
18 #define SAD1_RATE_MASK GENMASK(6, 0) /* bitfield of supported rates */
25 #define SAD1_RATE_192000_MASK BIT(6)
98 struct snd_interval *r = hw_param_interval(params, rule->var); in eld_limit_rates()
100 unsigned int rate_mask = 7, i; in eld_limit_rates()
101 const u8 *sad, *eld = rule->private; in eld_limit_rates()
107 for (i = drm_eld_sad_count(eld); i > 0; i--, sad += 3) { in eld_limit_rates()
114 if (c->min <= max_channels) in eld_limit_rates()
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