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/src/share/man/man4/
H A Dahc.491 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
93 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
94 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
95 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
96 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
97 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
98 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
99 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
100 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
101 .It "aic7895" Ta "15" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta "2 3 4 5"
[all …]
/src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm660.dtsi20 * 775MHz is only available on the highest speed bin
26 opp-hz = /bits/ 64 <750000000>;
37 opp-hz = /bits/ 64 <700000000>;
44 opp-hz = /bits/ 64 <647000000>;
51 opp-hz = /bits/ 64 <588000000>;
58 opp-hz = /bits/ 64 <465000000>;
65 opp-hz = /bits/ 64 <370000000>;
73 opp-hz = /bits/ 64 <266000000>;
80 opp-hz = /bits/ 64 <160000000>;
90 capacity-dmips-mhz = <1024>;
[all …]
H A Dsdm632.dtsi65 capacity-dmips-mhz = <1980>;
70 capacity-dmips-mhz = <1980>;
75 capacity-dmips-mhz = <1980>;
80 capacity-dmips-mhz = <1980>;
85 opp-hz = /bits/ 64 <725000000>;
/src/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-common.dtsi73 capacity-dmips-mhz = <714>;
87 capacity-dmips-mhz = <714>;
101 capacity-dmips-mhz = <1024>;
115 capacity-dmips-mhz = <1024>;
129 capacity-dmips-mhz = <1024>;
143 capacity-dmips-mhz = <1024>;
157 capacity-dmips-mhz = <1024>;
171 capacity-dmips-mhz = <1024>;
185 capacity-dmips-mhz = <1024>;
199 capacity-dmips-mhz = <1024>;
[all …]
H A Dt8015.dtsi63 capacity-dmips-mhz = <633>;
77 capacity-dmips-mhz = <633>;
91 capacity-dmips-mhz = <633>;
105 capacity-dmips-mhz = <633>;
119 capacity-dmips-mhz = <1024>;
133 capacity-dmips-mhz = <1024>;
160 opp-hz = /bits/ 64 <300000000>;
165 opp-hz = /bits/ 64 <453000000>;
170 opp-hz = /bits/ 64 <672000000>;
175 opp-hz = /bits/ 64 <972000000>;
[all …]
H A Dt8010.dtsi78 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
83 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
88 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
93 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
98 opp-hz = /bits/ 64 <756000000>;
103 opp-hz = /bits/ 64 <1056000000>;
108 opp-hz = /bits/ 64 <1356000000>;
113 opp-hz = /bits/ 64 <1644000000>;
118 opp-hz = /bits/ 64 <1944000000>;
124 opp-hz = /bits/ 64 <2244000000>;
[all …]
H A Dt8011.dtsi90 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
95 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
100 opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */
105 opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */
110 opp-hz = /bits/ 64 <804000000>;
115 opp-hz = /bits/ 64 <1140000000>;
120 opp-hz = /bits/ 64 <1548000000>;
125 opp-hz = /bits/ 64 <1956000000>;
130 opp-hz = /bits/ 64 <2316000000>;
137 opp-hz = /bits/ 64 <2400000000>;
H A Dt8012.dtsi78 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
83 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
88 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
93 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
98 opp-hz = /bits/ 64 <756000000>;
103 opp-hz = /bits/ 64 <1056000000>;
108 opp-hz = /bits/ 64 <1356000000>;
113 opp-hz = /bits/ 64 <1644000000>;
118 opp-hz = /bits/ 64 <1944000000>;
123 opp-hz = /bits/ 64 <2244000000>;
[all …]
/src/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroid-core.dtsi45 /* derived from 532MHz MPLL */
47 opp-hz = /bits/ 64 <88700000>;
51 opp-hz = /bits/ 64 <133000000>;
55 opp-hz = /bits/ 64 <177400000>;
59 opp-hz = /bits/ 64 <266000000>;
63 opp-hz = /bits/ 64 <532000000>;
71 /* derived from 666MHz CPLL */
73 opp-hz = /bits/ 64 <66600000>;
76 opp-hz = /bits/ 64 <74000000>;
79 opp-hz = /bits/ 64 <83250000>;
[all …]
/src/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxm.dtsi46 capacity-dmips-mhz = <1024>;
50 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
58 capacity-dmips-mhz = <1024>;
66 capacity-dmips-mhz = <1024>;
77 capacity-dmips-mhz = <1024>;
88 capacity-dmips-mhz = <1024>;
99 capacity-dmips-mhz = <1024>;
110 opp-hz = /bits/ 64 <125000000>;
114 opp-hz = /bits/ 64 <250000000>;
[all …]
/src/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1466 /* 5 GHz, channels 52..64 */ in ieee80211_freq_to_channel_ext()
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1707 case 2: /* channels 52,56,60,64; dfs */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1712 if (chan < 36 || chan > 64) in ieee80211_chan_to_freq_us()
[all …]
/src/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-r1.dts94 i-cache-line-size = <64>;
97 d-cache-line-size = <64>;
102 capacity-dmips-mhz = <1024>;
111 i-cache-line-size = <64>;
114 d-cache-line-size = <64>;
119 capacity-dmips-mhz = <1024>;
128 i-cache-line-size = <64>;
131 d-cache-line-size = <64>;
136 capacity-dmips-mhz = <578>;
145 i-cache-line-size = <64>;
[all …]
H A Djuno.dts93 i-cache-line-size = <64>;
96 d-cache-line-size = <64>;
101 capacity-dmips-mhz = <1024>;
111 i-cache-line-size = <64>;
114 d-cache-line-size = <64>;
119 capacity-dmips-mhz = <1024>;
129 i-cache-line-size = <64>;
132 d-cache-line-size = <64>;
137 capacity-dmips-mhz = <578>;
147 i-cache-line-size = <64>;
[all …]
H A Djuno-r2.dts94 i-cache-line-size = <64>;
97 d-cache-line-size = <64>;
102 capacity-dmips-mhz = <1024>;
112 i-cache-line-size = <64>;
115 d-cache-line-size = <64>;
120 capacity-dmips-mhz = <1024>;
130 i-cache-line-size = <64>;
133 d-cache-line-size = <64>;
138 capacity-dmips-mhz = <485>;
148 i-cache-line-size = <64>;
[all …]
/src/sys/contrib/dev/iwlwifi/fw/
H A Drs.c44 { "48", "64QAM 2/3"},
45 { "54", "64QAM 3/4"},
46 { "60", "64QAM 5/6"},
57 "20Mhz",
58 "40Mhz",
59 "80Mhz",
60 "160 Mhz",
61 "320Mhz",
/src/sys/contrib/device-tree/Bindings/mfd/
H A Dstmpe.txt14 - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
22 3 -> 64 clocks
28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
/src/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2-kryo-cpu.yaml121 capacity-dmips-mhz = <1024>;
141 capacity-dmips-mhz = <1024>;
156 capacity-dmips-mhz = <1024>;
176 capacity-dmips-mhz = <1024>;
214 opp-hz = /bits/ 64 <307200000>;
221 opp-hz = /bits/ 64 <1401600000>;
228 opp-hz = /bits/ 64 <1593600000>;
242 opp-hz = /bits/ 64 <307200000>;
249 opp-hz = /bits/ 64 <1804800000>;
256 opp-hz = /bits/ 64 <1900800000>;
[all …]
/src/sys/contrib/device-tree/Bindings/media/i2c/
H A Dsony,imx412.yaml30 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
89 link-frequencies = /bits/ 64 <600000000>;
H A Dsony,imx415.yaml31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
109 link-frequencies = /bits/ 64 <445500000>;
/src/sys/contrib/dev/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
[all …]
/src/sys/contrib/device-tree/Bindings/riscv/
H A Dcpus.yaml137 capacity-dmips-mhz:
140 DMIPS/MHz, relative to highest capacity-dmips-mhz
169 i-cache-block-size = <64>;
185 d-cache-block-size = <64>;
186 d-cache-sets = <64>;
191 i-cache-block-size = <64>;
192 i-cache-sets = <64>;
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso13 brightness-levels = <0 8 16 32 64 128 255>;
29 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
30 * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
31 * engine can reach accurate pixel clock of exactly 72.4 MHz.
/src/contrib/ntp/html/hints/
H A Dsolaris.xtra.402311810 The clock on a sun4u drifts unacceptably. On a typical 143 mHz Ultra,
16 it must be assured that the local clock drifts no more than 20 ms in 64
17 seconds; this particular 143 mHz Ultra will drift by nearly 9 ms in that
26 quite far from the actual ticks per second. Typical was the 143 mHz
/src/sys/contrib/dev/iwlwifi/fw/api/
H A Dphy-ctxt.h20 /* and 320 MHz for EHT */
27 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
31 * 40Mhz |____|____|
32 * 80Mhz |____|____|____|____|
33 * 160Mhz |____|____|____|____|____|____|____|____|
34 * 320MHz |____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|
145 * @sbb_bandwidth: 0 disabled, 1 - 40Mhz ... 4 - 320MHz
150 * @reserved: reserved to align to 64 bit
/src/sys/contrib/device-tree/Bindings/gpu/
H A Darm,mali-midgard.yaml106 power coefficient in units of uW/MHz/V^2. The
117 where voltage is in V, frequency is in MHz.
176 opp-hz = /bits/ 64 <533000000>;
180 opp-hz = /bits/ 64 <450000000>;
184 opp-hz = /bits/ 64 <400000000>;
188 opp-hz = /bits/ 64 <350000000>;
192 opp-hz = /bits/ 64 <266000000>;
196 opp-hz = /bits/ 64 <160000000>;
200 opp-hz = /bits/ 64 <100000000>;

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