/linux-5.10/Documentation/devicetree/bindings/iommu/ |
D | arm,smmu.yaml | 35 - description: Qcom SoCs implementing "arm,mmu-500" 38 - qcom,sc7180-smmu-500 39 - qcom,sdm845-smmu-500 40 - qcom,sm8150-smmu-500 41 - qcom,sm8250-smmu-500 42 - const: arm,mmu-500 43 - description: Marvell SoCs implementing "arm,mmu-500" 45 - const: marvell,ap806-smmu-500 46 - const: arm,mmu-500 47 - description: NVIDIA SoCs that program two ARM MMU-500s identically [all …]
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/linux-5.10/Documentation/userspace-api/media/v4l/ |
D | bayer.svg | 8 …500v-1e3h1e3v1e3h-500z" stroke="#00f"/></g></g><g id="g261" class="com.sun.star.drawing.CustomShap… 25 …500v-1e3h1e3v1e3h-500z" stroke="#00f"/></g></g><g id="g531" class="com.sun.star.drawing.CustomShap… 26 …500v-1e3h1e3v1e3h-500z" stroke="#0c0"/></g></g><g id="g552" class="com.sun.star.drawing.CustomShap… 27 …500v-1e3h1e3v1e3h-500z" stroke="#f00"/></g></g><g id="g573" class="com.sun.star.drawing.CustomShap… 28 …500v-1e3h1e3v1e3h-500z" stroke="#0c0"/></g></g><g id="g594" class="com.sun.star.drawing.CustomShap… 29 …500v-1e3h1e3v1e3h-500z" stroke="#f00"/></g></g><g id="g615" class="com.sun.star.drawing.CustomShap… 30 …500v-1e3h1e3v1e3h-500z" stroke="#f00"/></g></g><g id="g636" class="com.sun.star.drawing.CustomShap…
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/linux-5.10/drivers/net/wireless/broadcom/brcm80211/include/ |
D | brcmu_wifi.h | 170 /* defined rate in 500kbps */ 171 #define BRCM_MAXRATE 108 /* in 500kbps units */ 172 #define BRCM_RATE_1M 2 /* in 500kbps units */ 173 #define BRCM_RATE_2M 4 /* in 500kbps units */ 174 #define BRCM_RATE_5M5 11 /* in 500kbps units */ 175 #define BRCM_RATE_11M 22 /* in 500kbps units */ 176 #define BRCM_RATE_6M 12 /* in 500kbps units */ 177 #define BRCM_RATE_9M 18 /* in 500kbps units */ 178 #define BRCM_RATE_12M 24 /* in 500kbps units */ 179 #define BRCM_RATE_18M 36 /* in 500kbps units */ [all …]
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/linux-5.10/drivers/media/tuners/ |
D | mxl301rf.c | 118 { 64500, 500, 0x92, 0x07 }, 120 { 205500, 500, 0x2c, 0x04 }, 121 { 212500, 500, 0x1e, 0x04 }, 122 { 226500, 500, 0xd4, 0x07 }, 123 { 99143, 500, 0x9c, 0x07 }, 124 { 173143, 500, 0xd4, 0x07 }, 126 { 207143, 500, 0xce, 0x07 }, 127 { 225143, 500, 0xce, 0x07 }, 128 { 243143, 500, 0xd4, 0x07 }, 129 { 261143, 500, 0xd4, 0x07 }, [all …]
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/linux-5.10/arch/mips/boot/dts/cavium-octeon/ |
D | dlink_dsr-500n.dts | 3 * Device tree source for D-Link DSR-500N. 8 /include/ "dlink_dsr-500n-1000n.dtsi" 12 model = "dlink,dsr-500n"; 13 compatible = "dlink,dsr-500n", "cavium,octeon-3860";
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/linux-5.10/Documentation/admin-guide/device-mapper/ |
D | delay.rst | 23 # Create device delaying rw operation for 500ms 24 echo "0 `blockdev --getsz $1` delay $1 0 500" | dmsetup create delayed 29 # Create device delaying only write operation for 500ms and 31 echo "0 `blockdev --getsz $1` delay $1 0 0 $2 0 500" | dmsetup create delayed
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/linux-5.10/tools/time/ |
D | udelay_test.sh | 41 # 1..200, 200..500 (by 10), 500..2000 (by 100) 45 for (( delay = 200; delay < 500; delay += 10 )); do 48 for (( delay = 500; delay <= 2000; delay += 100 )); do
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/linux-5.10/drivers/iommu/arm/arm-smmu/ |
D | arm-smmu-impl.c | 118 * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before in arm_mmu500_reset() 135 * Disable MMU-500's not-particularly-beneficial next-page in arm_mmu500_reset() 220 if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") || in arm_smmu_impl_init() 221 of_device_is_compatible(np, "qcom,sc7180-smmu-500") || in arm_smmu_impl_init() 222 of_device_is_compatible(np, "qcom,sm8150-smmu-500") || in arm_smmu_impl_init() 223 of_device_is_compatible(np, "qcom,sm8250-smmu-500")) in arm_smmu_impl_init() 226 if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) in arm_smmu_impl_init()
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/linux-5.10/drivers/cpufreq/ |
D | sh-cpufreq.c | 40 return (clk_get_rate(&per_cpu(sh_cpuclk, cpu)) + 500) / 1000; in sh_cpufreq_get() 67 freqs.new = (freq + 500) / 1000; in __sh_cpufreq_target() 101 policy->min = (clk_round_rate(cpuclk, 1) + 500) / 1000; in sh_cpufreq_verify() 102 policy->max = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000; in sh_cpufreq_verify() 131 (clk_round_rate(cpuclk, 1) + 500) / 1000; in sh_cpufreq_cpu_init() 133 (clk_round_rate(cpuclk, ~0UL) + 500) / 1000; in sh_cpufreq_cpu_init()
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/linux-5.10/tools/perf/tests/ |
D | maps.c | 42 { "bpf_prog_2", 500, 600 }, in test__maps__merge_in() 48 { "kcore1", 300, 500 }, in test__maps__merge_in() 49 { "bpf_prog_2", 500, 600 }, in test__maps__merge_in() 57 { "kcore1", 300, 500 }, in test__maps__merge_in() 58 { "bpf_prog_2", 500, 600 }, in test__maps__merge_in()
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/linux-5.10/drivers/hwmon/ |
D | intel-m10-bmc-hwmon.c | 39 { 0x100, 0x104, 0x108, 0x10c, 0x0, 500, "Board Temperature" }, 40 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Die Temperature" }, 41 { 0x11c, 0x124, 0x120, 0x0, 0x0, 500, "QSFP0 Temperature" }, 42 { 0x12c, 0x134, 0x130, 0x0, 0x0, 500, "QSFP1 Temperature" }, 43 { 0x168, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A Temperature" }, 44 { 0x16c, 0x0, 0x0, 0x0, 0x0, 500, "Retimer A SerDes Temperature" }, 45 { 0x170, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B Temperature" }, 46 { 0x174, 0x0, 0x0, 0x0, 0x0, 500, "Retimer B SerDes Temperature" },
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/linux-5.10/drivers/clk/spear/ |
D | spear1340_clock.c | 171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ 192 {.div = 0x06062}, /* for vco1div2 = 500 MHz */ 205 * 250, 332, 400 or 500 MHz considering different possibilites of input 216 * 500 200 100 0x05000 217 * 500 250 125 0x04000 218 * 500 332 166 0x03031 219 * 500 400 200 0x02800 220 * 500 500 250 0x02000 226 * 600 500 250 0x02666 232 * 664 500 250 0x02A7E [all …]
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/linux-5.10/arch/arm64/boot/dts/ti/ |
D | k3-am654-industrial-thermal.dtsi | 7 polling-delay = <500>; /* milliseconds */ 21 polling-delay = <500>; /* milliseconds */ 35 polling-delay = <500>; /* milliseconds */
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/linux-5.10/Documentation/security/keys/ |
D | trusted-encrypted.rst | 122 -3 --alswrv 500 500 keyring: _ses 123 97833714 --alswrv 500 -1 \_ keyring: _uid.500 124 440502848 --alswrv 500 500 \_ trusted: kmk
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/linux-5.10/tools/testing/selftests/net/ |
D | udpgro.sh | 148 run_test "GRO with custom segment size" "${ipv4_args} -M 1 -s 14720 -S 500 " "-4 -n 1 -l 14720" 149 … "GRO with custom segment size cmsg" "${ipv4_args} -M 1 -s 14720 -S 500 " "-4 -n 1 -l 14720 -S 500" 159 run_test "GRO with custom segment size" "${ipv6_args} -M 1 -s 14520 -S 500" "-n 1 -l 14520" 160 …test "GRO with custom segment size cmsg" "${ipv6_args} -M 1 -s 14520 -S 500" "-n 1 -l 14520 -S 500"
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/linux-5.10/arch/mips/include/asm/ |
D | mc146818-time.h | 16 * For check timing call set_rtc_mmss() 500ms; used in timer interrupt. 23 * called 500 ms after the second nowtime has started, because when 25 * jump to the next second precisely 500 ms later. Check the Motorola 78 * update precisely 500 ms later. You won't find this mentioned in in mc146818_set_rtc_mmss()
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/linux-5.10/drivers/zorro/ |
D | zorro.ids | 103 0500 500 [SCSI Host Adapter and RAM Expansion] 104 0800 500 [SCSI Host Adapter] 105 0900 500XP/2000 [RAM Expansion] 106 0a00 500RX/2000 [RAM Expansion] 108 0c00 500XP/SupraDrive WordSync [SCSI Host Adapter] 189 0400 Oktagon 500 [SCSI Host Adapter] 236 0400 Oktagon 500 [SCSI Host Adapter] 380 0300 SCRAM 500 [SCSI Host Adapter] 381 0400 SCRAM 500 [RAM Expansion]
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/linux-5.10/drivers/mtd/ |
D | ssfdc.c | 47 NCylinder 125 125 250 250 500 500 500 500 67 { MiB( 16), 500, 4, 16 }, 68 { MiB( 32), 500, 8, 16 }, 69 { MiB( 64), 500, 8, 32 }, 70 { MiB(128), 500, 16, 32 },
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/linux-5.10/drivers/gpu/drm/gma500/ |
D | mdfld_intel_display.c | 253 udelay(500); in mdfld_disable_crtc() 258 /* FIXME_MDFLD PO - change 500 to 1 after PO */ in mdfld_disable_crtc() 307 /* FIXME_MDFLD PO - change 500 to 1 after PO */ in mdfld_crtc_dpms() 308 udelay(500); in mdfld_crtc_dpms() 313 /* FIXME_MDFLD PO - change 500 to 1 after PO */ in mdfld_crtc_dpms() 314 udelay(500); in mdfld_crtc_dpms() 439 udelay(500); in mdfld_crtc_dpms() 546 71, 35, 273, 136, 324, 418, 465, 488, 500, 506, /* 91 - 100 */ 890 /* FIXME_MDFLD PO - change 500 to 1 after PO */ in mdfld_crtc_mode_set() 891 udelay(500); in mdfld_crtc_mode_set() [all …]
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/linux-5.10/Documentation/devicetree/bindings/leds/ |
D | leds-netxbig.txt | 32 timers = <NETXBIG_LED_TIMER1 500 500 33 NETXBIG_LED_TIMER2 500 1000>;
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/linux-5.10/Documentation/devicetree/bindings/sound/ |
D | da7219.txt | 50 [<2>, <5>, <10>, <50>, <100>, <200>, <500>] 52 [<200>, <500>, <750>, <1000>] 54 [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>] 99 dlg,mic-det-thr = <500>;
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/linux-5.10/Documentation/devicetree/bindings/arm/socionext/ |
D | socionext,uniphier-system-cache.yaml | 68 cache-controller@500c0000 { 81 l2: cache-controller@500c0000 { 93 l3: cache-controller@500c8000 {
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/linux-5.10/drivers/media/usb/dvb-usb/ |
D | technisat-usb2.c | 8 * registered office is Witan Gate House 500 - 600 Witan Gate West, 214 NULL, 0, 500); 269 led, 8, 500); in technisat_usb2_set_led() 290 b, 1, 500); in technisat_usb2_set_led_timer() 328 msecs_to_jiffies(500)); in technisat_usb2_green_led_control() 355 version, 3, 500); in technisat_usb2_identify_state() 560 NULL, 0, 500); in technisat_usb2_frontend_attach() 627 buf, 5, 500); in technisat_usb2_get_ir() 637 buf, 62, 500); in technisat_usb2_get_ir() 773 msecs_to_jiffies(500)); in technisat_usb2_probe()
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/linux-5.10/Documentation/doc-guide/ |
D | svg_image.svg | 7 <rect x="100" y="100" width="500" height="200" fill="white" stroke="black" stroke-width="20px"/> 8 <line x1="180" y1="370" x2="500" y2="50" stroke="black" stroke-width="15px"/>
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/linux-5.10/drivers/gpu/drm/msm/dsi/pll/ |
D | dsi_pll_28nm.c | 165 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate() 166 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate() 338 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_hpm() 374 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_hpm() 405 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); in dsi_pll_28nm_enable_seq_lp() 408 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_lp() 411 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_lp() 415 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in dsi_pll_28nm_enable_seq_lp() 418 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); in dsi_pll_28nm_enable_seq_lp()
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