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/linux-6.15/tools/perf/pmu-events/arch/x86/arrowlake/
Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
12 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
13 "Counter": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
32 "Counter": "0,1,2,3,4,5,6,7",
40 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
41 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
[all …]
Dfrontend.json4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
24 "Counter": "0,1,2,3,4,5,6,7",
27 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
34 "Counter": "0,1,2,3,4,5,6,7,8,9",
37 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
44 "Counter": "0,1,2,3,4,5,6,7,8,9",
53 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/lunarlake/
Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 … but second level hits due to a demand load that did not start a page walk. Account for 4k page si…
41 "Counter": "0,1,2,3,4,5,6,7",
49 …ut second level hits due to a demand load that did not start a page walk. Account for large page s…
50 "Counter": "0,1,2,3,4,5,6,7",
[all …]
Dfrontend.json4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
42 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
[all …]
Dother.json3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
4 "Counter": "0,1,2,3,4,5,6,7,8,9",
7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
23 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr…
32 "Counter": "0,1,2,3,4,5,6,7",
35 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another…
41 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc…
42 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.15/drivers/ata/pata_parport/
Dkbic.c5 * This is a low-level driver for the KBIC-951A and KBIC-971A
9 * required for the 971A interferes with the correct operation of
10 * the 951A, so this driver registers itself twice, once for
25 #define j44(a, b) ((((a >> 4) & 0x0f) | (b & 0xf0)) ^ 0x88) argument
26 #define j53(w) (((w >> 3) & 0x1f) | ((w >> 4) & 0xe0))
37 int a, b, s; in kbic_read_regr() local
43 w0(regr | 0x18 | s); w2(4); w2(6); w2(4); w2(1); w0(8); in kbic_read_regr()
44 a = r1(); w0(0x28); b = r1(); w2(4); in kbic_read_regr()
45 return j44(a, b); in kbic_read_regr()
47 w0(regr|0x38 | s); w2(4); w2(6); w2(4); w2(5); w0(8); in kbic_read_regr()
[all …]
Depat.c20 #define j44(a, b) (((a >> 4) & 0x0f) + (b & 0xf0)) argument
21 #define j53(a, b) (((a >> 3) & 0x1f) + ((b << 4) & 0xe0)) argument
45 w0(0x60+r); w2(1); w0(val); w2(4); in epat_write_regr()
48 case 4: in epat_write_regr()
57 int a, b, r; in epat_read_regr() local
65 a = r1(); w2(4); b = r1(); in epat_read_regr()
66 return j44(a, b); in epat_read_regr()
68 w0(0x40+r); w2(1); w2(4); in epat_read_regr()
69 a = r1(); b = r2(); w0(0xff); in epat_read_regr()
70 return j53(a, b); in epat_read_regr()
[all …]
/linux-6.15/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S15 #define b_offset 4
28 /* define a few register aliases to allow macro substitution */
61 * a input register containing a (rotated 16)
65 * operations on a and b are interleaved to increase performance
67 #define encrypt_round(a,b,c,d,round)\ argument
69 mov s1(%r11,%rdi,4),%r8d;\
70 movzx a ## B, %edi;\
71 mov s2(%r11,%rdi,4),%r9d;\
74 xor s2(%r11,%rdi,4),%r8d;\
75 movzx a ## H, %edi;\
[all …]
Dtwofish-i586-asm_32.S17 #define ctx 4 /* Twofish context structure */
20 #define b_offset 4
33 /* define a few register aliases to allow macro substitution */
61 * a input register containing a (rotated 16)
65 * operations on a and b are interleaved to increase performance
67 #define encrypt_round(a,b,c,d,round)\ argument
70 mov s1(%ebp,%edi,4),d ## D;\
71 movzx a ## B, %edi;\
72 mov s2(%ebp,%edi,4),%esi;\
75 xor s2(%ebp,%edi,4),d ## D;\
[all …]
Dsha256-avx2-asm.S11 # This software is available to you under a choice of one of two
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
48 # This code schedules 2 blocks at a time, with 4 lanes per block
103 a = %eax define
116 _XFER_SIZE = 2*64*4 # 2 blocks, 64 rounds, 4 bytes/round
140 # Rotate values of symbols a...h
150 b = a
151 a = TMP_ define
157 mov a, y3 # y3 = a # MAJA
162 or c, y3 # y3 = a|c # MAJA
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/meteorlake/
Dvirtual-memory.json3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
27 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
34 "Counter": "0,1,2,3,4,5,6,7",
42 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
46 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
52 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
56 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
62 …cription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
[all …]
/linux-6.15/Documentation/userspace-api/media/v4l/
Dpixfmt-rgb.rst9 These formats encode each pixel as a triplet of RGB values. They are packed
12 bits required to store a pixel is not aligned to a byte boundary, the data is
20 or a permutation thereof, collectively referred to as alpha formats) depend on
24 a meaningful value. Otherwise, when the device doesn't capture an alpha channel
25 but can set the alpha bit to a user-configurable value, the
28 the value specified by that control. Otherwise a corresponding format without
34 filled with meaningful values by applications. Otherwise a corresponding format
38 Formats that contain padding bits are named XRGB (or a permutation thereof).
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
46 respectively. 'a' denotes bits of the alpha component (if supported by the
[all …]
/linux-6.15/include/uapi/drm/
Ddrm_fourcc.h4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
69 * a canonical pair needs to be defined and used by all drivers. Preferred
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/sierraforest/
Dvirtual-memory.json3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
19 …cription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
20 "Counter": "0,1,2,3,4,5,6,7",
23 …d in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes pag…
28 …iefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
29 "Counter": "0,1,2,3,4,5,6,7",
32 … missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag…
38 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/grandridge/
Dvirtual-memory.json3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4 "Counter": "0,1,2,3,4,5,6,7",
12 "Counter": "0,1,2,3,4,5,6,7",
19 …cription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
20 "Counter": "0,1,2,3,4,5,6,7",
23 …d in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes pag…
28 …iefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
29 "Counter": "0,1,2,3,4,5,6,7",
32 … missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag…
38 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.15/drivers/staging/greybus/Documentation/
Dsysfs-bus-greybus3 KernelVersion: 4.XX
7 where N is a dynamically assigned 1-based id.
11 KernelVersion: 4.XX
18 KernelVersion: 4.XX
21 A Module M on the bus N, where M is the 1-byte interface
26 KernelVersion: 4.XX
29 Writing a non-zero argument to this attibute disables the
34 KernelVersion: 4.XX
37 The ID of a Greybus module, corresponding to the ID of its
42 KernelVersion: 4.XX
[all …]
/linux-6.15/drivers/net/ethernet/sfc/
Dmcdi_pcol.h19 #define MC_FW_STATE_BOOTING (4)
24 * Unlike a warm boot, assume DMEM has been reloaded, so that
51 /* Check whether an mcfw version (in host order) belongs to a bootloader */
65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
87 * The protocol requires one response to be delivered for every request; a
102 #define MCDI_HEADER_SEQ_WIDTH 4
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
130 * Both events share a common structure:
148 * Events can be squirted out of the UART (using LOG_CTRL) without a
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/alderlaken/
Dcache.json3 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
4 "Counter": "0,1,2,3,4,5",
7 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
11 …ription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core bas…
12 "Counter": "0,1,2,3,4,5",
15 …Cache accesses that resulted in a hit from a front door request only (does not include rejects or …
20 …ription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core ba…
21 "Counter": "0,1,2,3,4,5",
24 …Cache accesses that resulted in a miss from a front door request only (does not include rejects or…
29 …"Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
[all …]
/linux-6.15/Documentation/input/devices/
Delantech.rst18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
33 7. Hardware version 4
39 8. Trackpoint (for Hardware version 3 and 4)
51 and version 4. Version 1 is found in "older" laptops and uses 4 bytes per
56 of up to 3 fingers. Hardware version 4 uses 6 bytes per packet, and can
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
[all …]
/linux-6.15/drivers/net/wireguard/selftest/
Dallowedips.c3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
8 * DEBUG_PRINT_TRIE_GRAPHVIZ to be 1, then every time there's a full tree in
9 * memory, it will be printed out as KERN_DEBUG in a format that can be passed
12 * randomized tests done against a trivial implementation, which may take
13 * upwards of a half-hour to complete. There's no set of users who should be
127 if (node->ip_version == 4) { in horrible_mask_self()
190 node->ip_version = 4; in horrible_allowedips_insert_v4()
220 if (node->ip_version == 4 && horrible_match_v4(node, ip)) in horrible_allowedips_lookup_v4()
287 get_random_bytes(ip, 4); in randomized_test()
301 memcpy(mutated, ip, 4); in randomized_test()
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/skylake/
Dvirtual-memory.json7 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1…
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
44 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
49 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
53 …4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and fu…
58 "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/cascadelakex/
Dvirtual-memory.json7 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1…
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
44 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
49 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
53 …4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and fu…
58 "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/skylakex/
Dvirtual-memory.json7 …PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1…
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
44 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
49 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
53 …4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and fu…
58 "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/alderlake/
Dvirtual-memory.json13 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
18 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
25 "Counter": "0,1,2,3,4,5",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
38 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
48 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
54 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
58 …4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and fu…
64 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
[all …]
/linux-6.15/drivers/net/ethernet/sfc/siena/
Dmcdi_pcol.h19 #define MC_FW_STATE_BOOTING (4)
24 * Unlike a warm boot, assume DMEM has been reloaded, so that
51 /* Check whether an mcfw version (in host order) belongs to a bootloader */
65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
87 * The protocol requires one response to be delivered for every request, a
102 #define MCDI_HEADER_SEQ_WIDTH 4
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
130 * Both events share a common structure:
148 * Events can be squirted out of the UART (using LOG_CTRL) without a
[all …]

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