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/kvm-unit-tests/x86/
H A Dtrampolines.S2 * Common bootstrapping code to transition from 16-bit to 32-bit code, and to
3 * transition from 32-bit to 64-bit code (x86-64 only)
5 #include "apic-defs.h"
23 lgdtl ap_rm_gdt_descr - sipi_entry
33 .word gdt32_end - gdt32 - 1
41 /* The 32-bit => 64-bit trampoline is x86-64 only. */
46 * EFI builds with "-shared -fPIC" and so cannot directly reference any absolute
47 * address. In 64-bit mode, RIP-relative addressing neatly solves the problem,
48 * but 32-bit code doesn't have that luxury. Make a dummy CALL to get RIP into
49 * a GPR in order to emulate RIP-relative for 32-bit transition code.
[all …]
H A Dmsr.c41 // read-only: 7, 11, 12
62 * Special case EFER since clearing LME/LMA is not allowed in 64-bit mode, in __test_msr_rw()
63 * and conversely setting those bits on 32-bit CPUs is not allowed. Treat in __test_msr_rw()
78 (u32)(r >> 32), (u32)r, (u32)(val >> 32), (u32)val); in __test_msr_rw()
127 if (is_64bit_host || !msr->is_64bit_only) { in test_msr()
128 __test_msr_rw(msr->index, msr->name, msr->value, msr->keep); in test_msr()
131 * The 64-bit only MSRs that take an address always perform in test_msr()
134 if (msr->is_64bit_only && in test_msr()
135 msr->value == addr_64) in test_msr()
136 test_wrmsr_fault(msr->index, msr->name, NONCANONICAL); in test_msr()
[all …]
H A Dsyscall.c17 wrmsr(MSR_STAR, (uint64_t)cs << 32); in test_syscall_lazy_load()
28 * This uses 32-bit syscall/sysret because KVM emulates it on Intel processors.
29 * However, the same bug happens with 64-bit syscall/sysret if two vCPUs
36 code_segment_upon_db = regs->cs; in handle_db()
37 regs->rflags &= ~(1 << 8); in handle_db()
47 /* 32-bit, ring-3 part of test_syscall_tf */
68 wrmsr(MSR_STAR, ((uint64_t)USER_CS32 << 48) | ((uint64_t)KERNEL_CS64 << 32)); in test_syscall_tf()
75 * syscall to syscall32_target -> TF cleared and no singlestep in test_syscall_tf()
H A Dcstart64.S1 #include "apic-defs.h"
55 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags)
96 smp_stacktop: .long stacktop - per_cpu_size
102 .quad 0x00cf9b000000ffff // flat 32-bit code segment
103 .quad 0x00cf93000000ffff // flat 32-bit data segment
133 /* Check if 5-level paging has already enabled */
138 pushq $32
H A Dkvmclock.c18 * Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
19 * yielding a 64-bit result.
29 delta >>= -shift; in scale_delta()
43 : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) ); in scale_delta()
46 "mul %%rdx ; shrd $32,%%rdx,%%rax" in scale_delta()
70 u32 high = rem >> 32; in __div64_32()
72 /* Reduce the thing a bit first */ in __div64_32()
76 res = (u64) high << 32; in __div64_32()
77 rem -= (u64) (high*base) << 32; in __div64_32()
87 rem -= b; in __div64_32()
[all …]
H A Dvmx.c91 #define MASK(_bits) GENMASK_ULL((_bits) - 1, 0)
142 { MASK(32), PIN_CONTROLS },
143 { MASK(32), CPU_EXEC_CTRL0 },
144 { MASK(32), EXC_BITMAP },
145 { MASK(32), PF_ERROR_MASK },
146 { MASK(32), PF_ERROR_MATCH },
147 { MASK(32), CR3_TARGET_COUNT },
148 { MASK(32), EXI_CONTROLS },
149 { MASK(32), EXI_MSR_ST_CNT },
150 { MASK(32), EXI_MSR_LD_CNT },
[all …]
H A Dla57.c14 TEST_REGISTER_MSR /* upper 32 bits = msr address */
20 u32 msr = test_register >> 32; in get_test_register_value()
55 u32 msr = test_register >> 32; in set_test_register_value()
142 * breaks the wrmsr_safe macro (it uses GS for per-CPU data). in test_register_write()
144 if ((test_register >> 32) == MSR_GS_BASE && expect_success) in test_register_write()
180 /* Canonical 48 bit value should always succeed */ in test_register()
184 /* 57-canonical value will work on CPUs that *support* LA57 */ in test_register()
199 ((u64)(address) << 32)), force_emulation)
217 "Tested invpcid type 0 with 0x%lx value - %s", in __test_invpcid()
257 * only on Intel these instructions were extended to 64 bit. in __test_canonical_checks()
[all …]
/kvm-unit-tests/lib/x86/
H A Ddesc.h5 * selector 32-bit 64-bit
7 * 0x08 ring-0 code segment (32-bit) ring-0 code segment (64-bit)
8 * 0x10 ring-0 data segment (32-bit) ring-0 data segment (32/64-bit)
9 * 0x18 ring-0 code segment (P=0) ring-0 code segment (64-bit, P=0)
10 * 0x20 intr_alt_stack TSS ring-0 code segment (32-bit)
11 * 0x28 ring-0 code segment (16-bit) same
12 * 0x30 ring-0 data segment (16-bit) same
13 * 0x38 (0x3b) ring-3 code segment (32-bit) same
14 * 0x40 (0x43) ring-3 data segment (32-bit) ring-3 data segment (32/64-bit)
15 * 0x48 (0x4b) **unused** ring-3 code segment (64-bit)
[all …]
H A Ddesc.c6 #include "apic-defs.h"
8 /* Boot-related data structures */
14 .limit = sizeof(boot_idt) - 1,
22 {0xffff, 0, 0, .type_limit_flags = 0xcf9b}, /* flat 32-bit code segment */
23 {0xffff, 0, 0, .type_limit_flags = 0xcf93}, /* flat 32-bit data segment */
24 {0xffff, 0, 0, .type_limit_flags = 0xcf1b}, /* flat 32-bit code segment, not present */
26 {0xffff, 0, 0, .type_limit_flags = 0x8f9b}, /* 16-bit code segment */
27 {0xffff, 0, 0, .type_limit_flags = 0x8f93}, /* 16-bit data segment */
28 {0xffff, 0, 0, .type_limit_flags = 0xcffb}, /* 32-bit code segment (user) */
29 {0xffff, 0, 0, .type_limit_flags = 0xcff3}, /* 32-bit data segment (user) */
[all …]
H A Dsmp.c132 for (cpu = cpu_count() - 1; cpu >= 0; --cpu) in on_cpus()
180 (struct descriptor_table_ptr *) (&ap_rm_gdt_descr - &rm_trampoline); in setup_rm_gdt()
196 * | <GDT used for 16-bit -> 32-bit trasition> in setup_rm_gdt()
208 (struct descriptor_table_ptr *) (&ap_rm_gdt_descr - &rm_trampoline); in setup_rm_gdt()
209 rm_gdt_descr->base = (ulong) ((u32) (&ap_rm_gdt - &rm_trampoline)); in setup_rm_gdt()
210 rm_gdt_descr->limit = (u16) (&ap_rm_gdt_end - &ap_rm_gdt - 1); in setup_rm_gdt()
214 * building with -shared, and 2. rip-relative addressing is not supported in in setup_rm_gdt()
215 * 16-bit mode, the relocated address of ap_rm_gdt_descr needs to be stored at in setup_rm_gdt()
226 * Set up a call gate to the 32-bit entrypoint (ap_start32) within GDT, since in setup_rm_gdt()
227 * EFI may not load the 32-bit AP entrypoint (ap_start32) low enough in setup_rm_gdt()
[all …]
H A Dprocessor.h18 * Get a linear address by combining @addr with a non-canonical pattern in the
62 #define X86_CR0_PE BIT(X86_CR0_PE_BIT)
64 #define X86_CR0_MP BIT(X86_CR0_MP_BIT)
66 #define X86_CR0_EM BIT(X86_CR0_EM_BIT)
68 #define X86_CR0_TS BIT(X86_CR0_TS_BIT)
70 #define X86_CR0_ET BIT(X86_CR0_ET_BIT)
72 #define X86_CR0_NE BIT(X86_CR0_NE_BIT)
74 #define X86_CR0_WP BIT(X86_CR0_WP_BIT)
76 #define X86_CR0_AM BIT(X86_CR0_AM_BIT)
78 #define X86_CR0_NW BIT(X86_CR0_NW_BIT)
[all …]
/kvm-unit-tests/x86/efi/
H A Defistart64.S1 /* Startup code and pre-defined data structures */
3 #include "apic-defs.h"
4 #include "asm-generic/page.h"
5 #include "crt0-efi-x86_64.S"
58 .quad 0x00cf9b000000ffff // flat 32-bit code segment
59 .quad 0x00cf93000000ffff // flat 32-bit data segment
60 .quad 0 // call gate to 32-bit AP entrypoint
/kvm-unit-tests/lib/
H A Dpci.h49 * @bar_num in all BAR access functions below is the index of the 32-bit
52 * In cases where the BAR size is 64-bit, a caller should still provide
53 * @bar_num in terms of 32-bit words. For example, if a device has a 64-bit
54 * BAR#0 and a 32-bit BAR#1, then caller should provide 2 to address BAR#1,
58 * tries to address the middle of a 64-bit register.
77 * pci-testdev is a driver for the pci-testdev qemu pci device. The
85 * pci-testdev supports at least three types of tests (via mmio and
86 * portio BARs): no-eventfd, wildcard-eventfd and datamatch-eventfd
H A Dbitops.h17 #define BIT(nr) (1UL << (nr)) macro
29 * Create a contiguous bitmask starting at bit position @l and ending at
31 * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
34 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
37 (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
45 int num = BITS_PER_LONG - 1; in fls()
48 if (!(word & (~0ul << 32))) { in fls()
49 num -= 32; in fls()
50 word <<= 32; in fls()
53 if (!(word & (~0ul << (BITS_PER_LONG-16)))) { in fls()
[all …]
H A Dacpi.h7 * All tables and structures must be byte-packed to match the ACPI
26 ((uint64_t)(ACPI_SIGNATURE(c5, c6, c7, c8)) << 32))
35 u32 rsdt_physical_address; /* 32-bit physical address of RSDT */
37 u64 xsdt_physical_address; /* 64-bit physical address of XSDT */
71 u8 bit_offset; /* Bit offset within the register */
73 u64 address; /* 64-bit address of struct or register */
87 u8 reserved2; /* Reserved - must be zero */
108 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
109 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
110 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
[all …]
/kvm-unit-tests/lib/arm/asm/
H A Dgic-v3-its.h2 * ITS 32-bit stubs
12 #error Do not directly include <asm/gic-v3-its.h>. Include <asm/gic.h>
24 assert_msg(false, "not supported on 32-bit"); in its_init()
H A Dsysreg.h16 #define CR_P (1 << 4) /* 32-bit exception handler */
17 #define CR_D (1 << 5) /* 32-bit data address range */
27 #define CR_L4 (1 << 15) /* LDR pc can set T bit */
/kvm-unit-tests/s390x/
H A Dstsi.c1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <asm/asm-offsets.h>
29 report_prefix_pushf("set invalid r0 bit %d", i); in test_specs()
31 stsi(pagebuf, 0, BIT(63 - i), 0); in test_specs()
36 for (i = 32; i <= 47; i++) { in test_specs()
37 report_prefix_pushf("set invalid r1 bit %d", i); in test_specs()
39 stsi(pagebuf, 1, 0, BIT(63 - i)); in test_specs()
44 for (i = 0; i < 32; i++) { in test_specs()
45 report_prefix_pushf("r0 bit %d ignored", i); in test_specs()
46 cc = stsi(pagebuf, 3, 2 | BIT(63 - i), 2); in test_specs()
[all …]
/kvm-unit-tests/arm/
H A Dcstart64.S9 #include <asm/asm-offsets.h>
13 #include <asm/pgtable-hwdef.h>
19 #include "efi/crt0-efi-aarch64.S"
33 * Bootloader params are in x0-x3. See kernel doc
123 * w0 -- function_id
124 * x1 -- arg0
125 * x2 -- arg1
126 * x3 -- arg2
127 * x4 -- arg3
128 * x5 -- arg4
[all …]
/kvm-unit-tests/lib/x86/asm/
H A Dmemory_areas.h4 #define AREA_NORMAL_PFN BIT(36-12)
8 #define AREA_HIGH_PFN BIT(32-12)
12 #define AREA_LOW_PFN BIT(24-12)
H A Ddebugreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
8 * DR6_ACTIVE_LOW combines fixed-1 and active-low bits (e.g. RTM), and is also
15 #define DR6_TRAP0 BIT(0) /* DR0 matched */
16 #define DR6_TRAP1 BIT(1) /* DR1 matched */
17 #define DR6_TRAP2 BIT(2) /* DR2 matched */
18 #define DR6_TRAP3 BIT(3) /* DR3 matched */
21 #define DR6_BUS_LOCK BIT(11) /* Bus lock 0x800 */
22 #define DR6_BD BIT(13) /* General Detect 0x2000 */
23 #define DR6_BS BIT(14) /* Single-Step 0x4000 */
24 #define DR6_BT BIT(15) /* Task Switch 0x8000 */
[all …]
/kvm-unit-tests/powerpc/
H A Demulator.c18 regs->nip, *(uint32_t*)regs->nip); in program_check_handler()
21 /* the result is bit 16 to 19 of SRR1 in program_check_handler()
22 * bit 0: SRR0 contains the address of the next instruction in program_check_handler()
23 * bit 1: Trap in program_check_handler()
24 * bit 2: Privileged instruction in program_check_handler()
25 * bit 3: Illegal instruction in program_check_handler()
26 * bit 4: FP enabled exception type in program_check_handler()
29 *data = regs->msr >> 16; in program_check_handler()
31 regs->nip += 4; in program_check_handler()
40 regs->nip, *(uint32_t*)regs->nip); in heai_handler()
[all …]
/kvm-unit-tests/lib/linux/
H A Dpci_regs.h6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
42 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
50 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
85 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
86 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
87 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
88 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
89 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
90 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
95 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
[all …]
/kvm-unit-tests/lib/arm64/asm/
H A Dgic-v3-its.h2 * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h
12 #error Do not directly include <asm/gic-v3-its.h>. Include <asm/gic.h>
73 #define GITS_TYPER_PLPIS BIT(0)
74 #define GITS_TYPER_VLPIS BIT(1)
81 #define GITS_TYPER_PTA BIT(19)
82 #define GITS_TYPER_CIDBITS GENMASK_ULL(35, 32)
83 #define GITS_TYPER_CIDBITS_SHIFT 32
84 #define GITS_TYPER_CIL BIT(36)
90 #define GITS_BASER_VALID BIT(63)
91 #define GITS_BASER_INDIRECT BIT(62)
/kvm-unit-tests/riscv/
H A Dsbi-fwft.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "sbi-tests.h"
129 regs->epc += 4; in misaligned_handler()
174 #if __riscv_xlen > 32 in fwft_check_misaligned_exc_deleg()
175 ret = fwft_misaligned_exc_set(BIT(32), 0); in fwft_check_misaligned_exc_deleg()
177 "Set misaligned deleg with invalid value > 32bits"); in fwft_check_misaligned_exc_deleg()
179 ret = fwft_misaligned_exc_set(0, BIT(32)); in fwft_check_misaligned_exc_deleg()
181 "Set misaligned deleg with invalid flag > 32bits"); in fwft_check_misaligned_exc_deleg()
198 ".option arch,-c\n" in fwft_check_misaligned_exc_deleg()
206 * Even though the SBI delegated the misaligned exception to S-mode, it might not trap on in fwft_check_misaligned_exc_deleg()
[all …]

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