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/linux-6.15/tools/lib/
Dlist_sort.c8 * Returns a list organized in an intermediate format suited
12 __attribute__((nonnull(2,3,4)))
14 struct list_head *a, struct list_head *b) in merge() argument
19 /* if equal, take 'a' -- important for sort stability */ in merge()
20 if (cmp(priv, a, b) <= 0) { in merge()
21 *tail = a; in merge()
22 tail = &a->next; in merge()
23 a = a->next; in merge()
24 if (!a) { in merge()
33 *tail = a; in merge()
[all …]
/linux-6.15/lib/
Dlist_sort.c8 * Returns a list organized in an intermediate format suited
12 __attribute__((nonnull(2,3,4)))
14 struct list_head *a, struct list_head *b) in merge() argument
19 /* if equal, take 'a' -- important for sort stability */ in merge()
20 if (cmp(priv, a, b) <= 0) { in merge()
21 *tail = a; in merge()
22 tail = &a->next; in merge()
23 a = a->next; in merge()
24 if (!a) { in merge()
33 *tail = a; in merge()
[all …]
/linux-6.15/arch/powerpc/crypto/
Dmd5-asm.S61 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
69 add a,a,rT0; /* 1: a = a + f */ \
71 addis w1,w1,k1h; /* 2: wk = w + k */ \
72 add a,a,w0; /* 1: a = a + wk */ \
73 addi w1,w1,k1l; /* 2: wk = w + k' */ \
74 rotrwi a,a,p; /* 1: a = a rotl x */ \
75 add d,d,w1; /* 2: a = a + wk */ \
76 add a,a,b; /* 1: a = a + b */ \
77 and rT0,a,b; /* 2: f = b and c */ \
78 andc rT1,c,a; /* 2: f' = ~b and d */ \
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/skylake/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/cascadelakex/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/skylakex/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/ivytown/
Duncore-power.json4 "Counter": "0,1,2,3",
7a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
74 "BriefDescription": "Core 2 C State Transition Cycles",
[all …]
/linux-6.15/arch/x86/crypto/
Dsha256-ssse3-asm.S11 # This software is available to you under a choice of one of two
13 # General Public License (GPL) Version 2, available from the file
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
92 INP = %rsi # 2nd arg
100 a = %eax define
135 # Rotate values of symbols a...h
144 b = a
145 a = TMP_ define
149 ## compute s0 four at a time and s1 two at a time
150 ## compute W[-16] + W[-7] 4 at a time
[all …]
Dsha256-avx-asm.S11 # This software is available to you under a choice of one of two
13 # General Public License (GPL) Version 2, available from the file
32 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
47 # This code schedules 1 block at a time, with 4 lanes per block
99 INP = %rsi # 2nd arg
107 a = %eax define
141 # Rotate values of symbols a...h
150 b = a
151 a = TMP_ define
155 ## compute s0 four at a time and s1 two at a time
[all …]
/linux-6.15/arch/sparc/crypto/
Dopcodes.h18 #define CRC32C(a,b,c) \ argument
19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
30 #define AES_EROUND01(a,b,c,d) \ argument
31 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
32 #define AES_EROUND23(a,b,c,d) \ argument
33 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
34 #define AES_DROUND01(a,b,c,d) \ argument
35 .word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d));
36 #define AES_DROUND23(a,b,c,d) \ argument
37 .word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d));
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/linux-6.15/tools/perf/pmu-events/arch/x86/meteorlake/
Dvirtual-memory.json3 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
22 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
23 "Counter": "0,1,2,3",
27 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
34 "Counter": "0,1,2,3,4,5,6,7",
42 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
43 "Counter": "0,1,2,3",
46 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/sapphirerapids/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
35 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/emeraldrapids/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
35 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/graniterapids/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
35 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/tigerlake/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
35 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/icelakex/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
35 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/rocketlake/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
35 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/icelake/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
35 …ions missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.15/drivers/input/serio/
DKconfig11 * standard AT keyboard and PS/2 mouse *
17 To compile this driver as a module, choose M here: the
24 the architecture might use a PC serio device (i8042) to
34 i8042 is the chip over which the standard AT keyboard and PS/2
40 To compile this driver as a module, choose M here: the
55 To compile this driver as a module, choose M here: the
62 Say Y here if you have a Texas Instruments TravelMate notebook
63 equipped with the ct82c710 chip and want to use a mouse connected
68 To compile this driver as a module, choose M here: the
79 Say Y here if you built a simple parallel port adapter to attach
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/linux-6.15/tools/perf/pmu-events/arch/x86/lunarlake/
Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 … but second level hits due to a demand load that did not start a page walk. Account for 4k page si…
41 "Counter": "0,1,2,3,4,5,6,7",
49 …ut second level hits due to a demand load that did not start a page walk. Account for large page s…
50 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/
Dl2_cache.json4 …"PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is
8 …"PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified…
12 …are not counted. Data would not be written outside the cache when invalidating a clean cache line."
16 …"PublicDescription": "Counts level 2 cache line allocates that do not fetch data from outside the …
20 …ublicDescription": "Counts accesses to the level 2 cache due to instruction accesses. Level 2 cach…
24 …"PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified…
28 …"PublicDescription": "Counts level 2 data cache accesses due to memory read operations. Level 2 ca…
32 …"PublicDescription": "Counts level 2 cache accesses due to memory write operations. Level 2 cache …
36 … accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache f…
40 …accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache f…
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/arrowlake/
Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
12 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
13 "Counter": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
32 "Counter": "0,1,2,3,4,5,6,7",
40 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
41 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
[all …]
/linux-6.15/tools/perf/pmu-events/arch/x86/alderlake/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
13 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
14 "Counter": "0,1,2,3",
18 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
25 "Counter": "0,1,2,3,4,5",
34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
35 "Counter": "0,1,2,3",
38 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
44 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
45 "Counter": "0,1,2,3",
[all …]
/linux-6.15/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
Dcache.json1172 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This even…
1202 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This even…
123 …gardless of whether they allocate. If either the core is configured without a per-core L2 or the c…
126 …gardless of whether they allocate. If either the core is configured without a per-core L2 or the c…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
153 …"PublicDescription": "Level 2 TLB last-level walk cache access. This event does not count if the M…
156 …"BriefDescription": "Level 2 TLB last-level walk cache access. This event does not count if the MM…
159 …"PublicDescription": "Level 2 TLB last-level walk cache refill. This event does not count if the M…
162 …"BriefDescription": "Level 2 TLB last-level walk cache refill. This event does not count if the MM…
[all …]
/linux-6.15/drivers/input/mouse/
DKconfig9 Say Y here, and a list of supported mice will be displayed.
17 tristate "PS/2 mouse"
24 Say Y here if you have a PS/2 mouse connected to your system. This
25 includes the standard 2 or 3-button PS/2 mouse, as well as PS/2
30 in a specialized Xorg/XFree86 driver at:
32 and a new version of GPM at:
39 To compile this driver as a module, choose M here: the
43 bool "ALPS PS/2 mouse protocol extension" if EXPERT
47 Say Y here if you have an ALPS PS/2 touchpad connected to
53 bool "BYD PS/2 mouse protocol extension" if EXPERT
[all …]

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