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/qemu/tests/tcg/hexagon/
H A Dmisc.c82 "if (p0) memb(%1+#4)=#27\n\t" in S4_storeirbt_io()
90 "if (!p0) memb(%1+#4)=#27\n\t" in S4_storeirbf_io()
99 " if (p0.new) memb(%1+#4)=#27\n\t" in S4_storeirbtnew_io()
109 " if (!p0.new) memb(%1+#4)=#27\n\t" in S4_storeirbfnew_io()
118 "if (p0) memh(%1+#4)=#27\n\t" in S4_storeirht_io()
126 "if (!p0) memh(%1+#4)=#27\n\t" in S4_storeirhf_io()
135 " if (p0.new) memh(%1+#4)=#27\n\t" in S4_storeirhtnew_io()
145 " if (!p0.new) memh(%1+#4)=#27\n\t" in S4_storeirhfnew_io()
154 "if (p0) memw(%1+#4)=#27\n\t" in S4_storeirit_io()
162 "if (!p0) memw(%1+#4)=#27\n\t" in S4_storeirif_io()
[all …]
/qemu/tests/tcg/alpha/system/
H A Dboot.S198 * the result is in $27. Register $28 may be clobbered; everything else
227 #define quotient $27
286 mov $28, $27
322 subq $31, $27, $23
324 cmovlt $28, $23, $27
363 subq $31, $28, $27
364 cmovge $24, $28, $27
389 addl $27, 0, $27
417 addl $28, 0, $27
456 subl $31, $27, $23
[all …]
/qemu/hw/pci-host/
H A Dversatile.c42 * QEMU behaviour, so they use IRQ 27 for all slots
55 * 27 nor 91 to slot zero's PCI_INTERRUPT_LINE register to
60 * 0 | 29 | 27 | 27 | 91
61 * 1 | 30 | 27 | 28 | 92
62 * 2 | 27 | 27 | 29 | 93
63 * 3 | 28 | 27 | 30 | 94
267 if (irq == 27) { in pci_vpb_broken_irq()
277 if (irq == slot + 27) { in pci_vpb_broken_irq()
281 if (irq == slot + 27 + 64) { in pci_vpb_broken_irq()
335 * Our output irqs 0..3 correspond to the baseboard's 27..30. in pci_vpb_map_irq()
H A Dmv64361.c181 MV64361_IRQ_P1_GPP24_31 = 27,
548 ret = BIT(27); in mv64361_read()
616 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
629 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
644 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
659 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
674 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
689 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
699 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
714 if (!(s->cpu_conf & BIT(27))) { in mv64361_write()
[all …]
/qemu/target/riscv/
H A Dinstmap.h154 (MASK_OP_MAJOR(op) | (op & (0x1F << 27)))
157 OPC_RISC_LR = OPC_RISC_ATOMIC | (0x02 << 27),
158 OPC_RISC_SC = OPC_RISC_ATOMIC | (0x03 << 27),
159 OPC_RISC_AMOSWAP = OPC_RISC_ATOMIC | (0x01 << 27),
160 OPC_RISC_AMOADD = OPC_RISC_ATOMIC | (0x00 << 27),
161 OPC_RISC_AMOXOR = OPC_RISC_ATOMIC | (0x04 << 27),
162 OPC_RISC_AMOAND = OPC_RISC_ATOMIC | (0x0C << 27),
163 OPC_RISC_AMOOR = OPC_RISC_ATOMIC | (0x08 << 27),
164 OPC_RISC_AMOMIN = OPC_RISC_ATOMIC | (0x10 << 27),
165 OPC_RISC_AMOMAX = OPC_RISC_ATOMIC | (0x14 << 27),
[all …]
/qemu/target/tricore/
H A Dtricore-opcodes.h88 #define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
93 #define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
104 #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
115 #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
122 (MASK_BITS_SHIFT(op, 22, 27) << 10))
125 (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
157 #define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
165 #define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
174 #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
183 #define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
[all …]
/qemu/hw/intc/
H A Dpnv_xive_regs.h101 #define PC_AT_KILL_BLOCK_ID PPC_BITMASK(27, 31)
113 #define PC_SCRUB_BLOCK_ID PPC_BITMASK(27, 31)
118 #define PC_VPC_CWATCH_BLOCKID PPC_BITMASK(27, 31)
155 #define VC_KILL_BLOCK_ID PPC_BITMASK(27, 31)
216 #define VST_TABLE_BLOCK PPC_BITMASK(27, 31)
H A Dxlnx-zynqmp-ipi.c51 FIELD(IPI_TRIG, PL_3, 27, 1)
63 FIELD(IPI_OBS, PL_3, 27, 1)
75 FIELD(IPI_ISR, PL_3, 27, 1)
87 FIELD(IPI_IMR, PL_3, 27, 1)
99 FIELD(IPI_IER, PL_3, 27, 1)
111 FIELD(IPI_IDR, PL_3, 27, 1)
135 int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27};
H A Dxlnx-pmu-iomod-intc.c82 FIELD(GPO3, PL_GPO_27, 27, 1)
115 FIELD(GPI0, RFT_COMPARE_ERR_12, 27, 1)
190 FIELD(GPI3, PL_GPI_27, 27, 1)
222 FIELD(IRQ_STATUS, PWR_UP_REQ, 27, 1)
246 FIELD(IRQ_PENDING, PWR_UP_REQ, 27, 1)
270 FIELD(IRQ_ENABLE, PWR_UP_REQ, 27, 1)
294 FIELD(IRQ_ACK, PWR_UP_REQ, 27, 1)
/qemu/target/mips/
H A Dcpu.h114 #define CP0MVPC0_PCP 27
220 * Register 24 Register 25 Register 26 Register 27
273 #define CP0_REGISTER_27 27
429 /* CP0 Register 27 */
481 #define CP0TCSt_TMX 27
631 #define CP0PG_IEC 27
697 #define CP0PC_XS 27
769 #define CP0St_RP 27
812 #define CP0Ca_DC 27
837 #define CP0C0_KU 25 /* 27..25 */
[all …]
/qemu/include/hw/misc/
H A Daspeed_scu.h103 * 27 2D Engine GCLK clock source selection
162 * 28:27 DRAM size setting (for VGA driver use)
187 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27)
188 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
269 * 27 Enable fast reset mode for ARM ICE debugger
301 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27)
385 * 27:25 RGMIICLK_DIV
/qemu/linux-user/ppc/
H A Dvdso.S118 .cfi_offset 27, 27 * sizeof_reg
154 .cfi_offset 59, offsetof_mcontext_fregs + 27 * sizeof_freg
213 save_vreg 27
/qemu/linux-user/hppa/
H A Dvdso.S83 .cfi_offset 27, offsetof_sigcontext_gr + 27 * 4
136 .cfi_offset 78, offsetof_sigcontext_fr + 27 * 8
137 .cfi_offset 79, offsetof_sigcontext_fr + 27 * 8 + 4
/qemu/linux-user/loongarch64/
H A Dvdso.S84 .cfi_offset 27, B_GR + 27 * 8
118 .cfi_offset 59, B_FR + 27 * 8
/qemu/gdb-xml/
H A Drx-core.xml35 <field name="IPL" start="24" end="27"/>
53 <field name="FO" start="27" end="27"/>
/qemu/include/hw/ssi/
H A Dpnv_spi_regs.h49 #define SPI_CLK_CFG_RST_CTRL PPC_BITMASK(24, 27)
76 #define SPI_STS_SHIFTER_FSM PPC_BITMASK(16, 27)
91 * Status reg bits 16-27 -> field bits 0-11
/qemu/hw/dma/
H A Dxlnx-zynq-devcfg.c52 FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
96 FIELD(INT_STS, PSS_CFG_RESET_B, 27, 1)
300 .ro = MAKE_64BIT_MASK(27, 64 - 27) },
302 .ro = MAKE_64BIT_MASK(27, 64 - 27),
/qemu/include/hw/usb/
H A Ddwc2-regs.h48 #define GOTGCTL_CHIRPEN BIT(27)
96 #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
144 #define GINTSTS_LPMTRANRCVD BIT(27)
393 #define ADPCTL_AR_MASK (0x3 << 27)
394 #define ADPCTL_AR_SHIFT 27
555 #define DXEPCTL_SNAK BIT(27)
650 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
651 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
720 #define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
721 #define TXSTS_QTOP_CHNEP_SHIFT 27
[all …]
/qemu/linux-user/riscv/
H A Dvdso.S142 .cfi_offset 27, B_GR + 27 * sizeof_reg
175 .cfi_offset 59, B_FR + 27 * sizeof_freg
/qemu/tests/tcg/tricore/asm/
H A Dtest_dextr.S33 TEST_D_DDI(dextr, 27, 0x048d159e, 0xabcdef01, 0x23456789, 26)
34 TEST_D_DDI(dextr, 28, 0x091a2b3c, 0xabcdef01, 0x23456789, 27)
69 TEST_D_DDD(dextr, 61, 0x091a2b3c, 0xabcdef01, 0x23456789, 27)
/qemu/tests/tcg/arm/
H A Dfcvt.ref58 27 SINGLE: 3.40282346638528859812e+38 / 0x7f7fffff (0 => OK)
59 27 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
121 27 SINGLE: 3.40282346638528859812e+38 / 0x7f7fffff (0 => OK)
122 27 DOUBLE: 3.40282346638528859812e+38 / 0x0047efffffe0000000 (0 => OK)
184 27 DOUBLE: 6.55030000000000000000e+04 / 0x0040effbe000000000 (0 => OK)
185 27 HALF: 0xffdf (0 => OK)
267 27 DOUBLE: 6.55030000000000000000e+04 / 0x0040effbe000000000 (0 => OK)
268 27 SINGLE: 6.55030000000000000000e+04 / 0x477fdf00 (0 => OK)
421 27 SINGLE: 3.40282346638528859812e+38 / 0x7f7fffff (0 => OK)
422 27 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
[all …]
/qemu/tests/tcg/aarch64/
H A Dfcvt.ref58 27 SINGLE: 3.40282346638528859812e+38 / 0x7f7fffff (0 => OK)
59 27 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
121 27 SINGLE: 3.40282346638528859812e+38 / 0x7f7fffff (0 => OK)
122 27 DOUBLE: 3.40282346638528859812e+38 / 0x0047efffffe0000000 (0 => OK)
184 27 DOUBLE: 6.55030000000000000000e+04 / 0x0040effbe000000000 (0 => OK)
185 27 HALF: 0x7bff (0x10 => INEXACT )
267 27 DOUBLE: 6.55030000000000000000e+04 / 0x0040effbe000000000 (0 => OK)
268 27 SINGLE: 6.55030000000000000000e+04 / 0x477fdf00 (0 => OK)
421 27 SINGLE: 3.40282346638528859812e+38 / 0x7f7fffff (0 => OK)
422 27 HALF: 0x7c00 (0x14 => OVERFLOW INEXACT )
[all …]
/qemu/target/hexagon/
H A Darch.c66 {27, 33, 39, 45},
70 {22, 27, 32, 37},
73 {19, 23, 27, 31},
76 {16, 20, 23, 27},
103 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
115 23, 24, 24, 25, 26, 26, 27, 27, 28, 29,
/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc115 { "LLR_BUF_2", 27, 1 },
722 tie_t = (val << 27) >> 30;
997 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
1005 tie_t = (val << 27) >> 27;
1196 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
1197 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1207 tie_t = (val << 26) >> 27;
1382 tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27);
1390 tie_t = (val << 27) >> 27;
1629 tie_t = (val << 27) >> 28;
[all …]
/qemu/disas/
H A Driscv-xthead.c477 switch ((inst >> 27) & 0b11111) { in decode_xtheadfmemidx()
485 switch ((inst >> 27) & 0b11111) { in decode_xtheadfmemidx()
580 switch ((inst >> 27) & 0b11111) { in decode_xtheadmemidx()
608 case 27: op = rv_op_th_lwuia; break; in decode_xtheadmemidx()
612 switch ((inst >> 27) & 0b11111) { in decode_xtheadmemidx()
654 switch ((inst >> 27) & 0b11111) { in decode_xtheadmempair()
661 switch ((inst >> 27) & 0b11111) { in decode_xtheadmempair()

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