25 (full) in projects: qemu - OpenGrok search results

Searched full:25 (Results 1 – 25 of 506) sorted by relevance

/qemu/target/riscv/
H A D	instmap.h	57 (0x7F << 25)))) 59 OPC_RISC_ADD = OPC_RISC_ARITH \| (0x0 << 12) \| (0x00 << 25), 60 OPC_RISC_SUB = OPC_RISC_ARITH \| (0x0 << 12) \| (0x20 << 25), 61 OPC_RISC_SLL = OPC_RISC_ARITH \| (0x1 << 12) \| (0x00 << 25), 62 OPC_RISC_SLT = OPC_RISC_ARITH \| (0x2 << 12) \| (0x00 << 25), 63 OPC_RISC_SLTU = OPC_RISC_ARITH \| (0x3 << 12) \| (0x00 << 25), 64 OPC_RISC_XOR = OPC_RISC_ARITH \| (0x4 << 12) \| (0x00 << 25), 65 OPC_RISC_SRL = OPC_RISC_ARITH \| (0x5 << 12) \| (0x00 << 25), 66 OPC_RISC_SRA = OPC_RISC_ARITH \| (0x5 << 12) \| (0x20 << 25), 67 OPC_RISC_OR = OPC_RISC_ARITH \| (0x6 << 12) \| (0x00 << 25), [all …]
/qemu/tests/tcg/alpha/system/
H A D	boot.S	`197 * These do not follow the C calling convention. Arguments are in $24+$25, 231 mov $25, divisor 234 beq $25, 9f 301 bis $24, $25, $28 308 stq $25, 16($sp) 313 subq $31, $25, $28 314 cmovlt $25, $28, $25 319 ldq $25, 16($sp) 323 xor $24, $25, $28 341 bis $24, $25, $28 [all …]`
/qemu/include/hw/misc/
H A D	xlnx-versal-crl.h	`41 FIELD(RPLL_CFG, LOCK_DLY, 25, 7) 56 FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) 60 FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) 64 FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) 71 FIELD(CPU_R5_CTRL, CLKACT, 25, 1) 75 FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) 81 FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) 87 FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) 91 FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) 95 FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) [all …]`
H A D	aspeed_scu.h	`105 * 25:23 APB PCLK divider selection 164 * 23 Enable 25 MHz reference clock input 271 * 25 Enable eSPI mode 273 * 23 Select 25 MHz reference clock input mode 303 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 340 * 25 Enable H-PLL reset 347 * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1) 349 * The default frequency is 1200Mhz when CLKIN = 25MHz 385 * 27:25 RGMIICLK_DIV`
H A D	xlnx-zynqmp-crf.h	`38 FIELD(APLL_CFG, LOCK_DLY, 25, 7) 58 FIELD(DPLL_CFG, LOCK_DLY, 25, 7) 78 FIELD(VPLL_CFG, LOCK_DLY, 25, 7) 103 FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1) 136 FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)`
/qemu/docs/specs/
H A D	riscv-aia.rst	`39 :widths: 25 25 25 25 25 25 25`
/qemu/tests/tcg/ppc64le/
H A D	float_madds.ref	56 …000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) 57 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) 58 op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) +… 60 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f… 62 …00p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p… 63 res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) 64 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … 66 …2(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0… 67 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) 68 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … [all …]
H A D	float_convs.ref	68 from single: f32(0x1.00000000000000000000p-25:0x33000000) 69 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 74 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 75 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 255 from single: f32(0x1.00000000000000000000p-25:0x33000000) 256 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 261 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 262 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 442 from single: f32(0x1.00000000000000000000p-25:0x33000000) 443 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) [all …]
/qemu/tests/tcg/aarch64/
H A D	float_madds.ref	56 …000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) 57 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) 58 op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) +… 60 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f… 62 …00p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p… 63 res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) 64 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … 66 …2(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0… 67 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) 68 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … [all …]
H A D	bti-3.c	`14 asm("mov %w0,#1; adr x16, 1f; br x16; 1: hint #25; mov %w0,#0" \ 18 asm("mov %w0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %w0,#0" \ 22 asm("mov %w0,#1; adr x15, 1f; br x15; 1: hint #25; mov %w0,#0" \`
H A D	float_convs.ref	68 from single: f32(0x1.00000000000000000000p-25:0x33000000) 69 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 74 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 75 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 255 from single: f32(0x1.00000000000000000000p-25:0x33000000) 256 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 261 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 262 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 442 from single: f32(0x1.00000000000000000000p-25:0x33000000) 443 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) [all …]
/qemu/tests/tcg/hexagon/
H A D	float_madds.ref	56 …000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) 57 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) 58 op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) +… 60 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f… 62 …00p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p… 63 res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) 64 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … 66 …2(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0… 67 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) 68 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … [all …]
H A D	float_convs.ref	68 from single: f32(0x1.00000000000000000000p-25:0x33000000) 69 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 74 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 75 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 255 from single: f32(0x1.00000000000000000000p-25:0x33000000) 256 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 261 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 262 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 442 from single: f32(0x1.00000000000000000000p-25:0x33000000) 443 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) [all …]
/qemu/tests/tcg/loongarch64/
H A D	float_madds.ref	56 …000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) 57 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) 58 op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) +… 60 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f… 62 …00p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p… 63 res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) 64 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … 66 …2(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0… 67 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) 68 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … [all …]
H A D	float_convs.ref	68 from single: f32(0x1.00000000000000000000p-25:0x33000000) 69 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 74 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 75 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 255 from single: f32(0x1.00000000000000000000p-25:0x33000000) 256 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 261 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 262 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 442 from single: f32(0x1.00000000000000000000p-25:0x33000000) 443 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) [all …]
/qemu/tests/tcg/arm/
H A D	float_madds.ref	56 …000) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0x1.00000000000000000000p-25:0x33000000) 57 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=OK (9/0) 58 op : f32(0x1.00000000000000000000p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) +… 60 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x0.00000000000000000000p+0:0000000000) + f… 62 …00p-126:0x00800000) * f32(0x1.00000000000000000000p-25:0x33000000) + f32(0x1.ffffe600000000000000p… 63 res: f32(0x1.ffffe600000000000000p-25:0x337ffff3) flags=INEXACT (10/0) 64 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … 66 …2(0x1.ffffe600000000000000p-25:0x337ffff3) * f32(0x1.00000000000000000000p-126:0x00800000) + f32(0… 67 res: f32(0x1.00000000000000000000p-25:0x33000000) flags=INEXACT (10/2) 68 op : f32(0x1.00000000000000000000p-25:0x33000000) * f32(0x1.ffffe600000000000000p-25:0x337ffff3) + … [all …]
H A D	float_convs.ref	68 from single: f32(0x1.00000000000000000000p-25:0x33000000) 69 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 74 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 75 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 255 from single: f32(0x1.00000000000000000000p-25:0x33000000) 256 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 261 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 262 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 442 from single: f32(0x1.00000000000000000000p-25:0x33000000) 443 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) [all …]
/qemu/include/hw/usb/
H A D	dwc2-regs.h	`98 #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25) 146 #define GINTSTS_HCHINT BIT(25) 176 #define GRXSTS_FN_MASK (0x7f << 25) 177 #define GRXSTS_FN_SHIFT 25 221 #define GI2CCTL_I2CSUSPCTL BIT(25) 306 #define GHWCFG4_DED_FIFO_EN BIT(25) 307 #define GHWCFG4_DED_FIFO_SHIFT 25 335 #define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25) 336 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25 396 #define ADPCTL_ADP_SNS_INT_MSK BIT(25) [all …]`
/qemu/target/sh4/
H A D	gdbstub.c	`58 case 25 ... 40: in superh_cpu_gdb_read_register() 62 return gdb_get_reg32(mem_buf, env->fregs[n - 25]); in superh_cpu_gdb_read_register() 118 case 25 ... 40: in superh_cpu_gdb_write_register() 122 env->fregs[n - 25] = ldl_p(mem_buf); in superh_cpu_gdb_write_register()`
/qemu/hw/intc/
H A D	xlnx-zynqmp-ipi.c	`53 FIELD(IPI_TRIG, PL_1, 25, 1) 65 FIELD(IPI_OBS, PL_1, 25, 1) 77 FIELD(IPI_ISR, PL_1, 25, 1) 89 FIELD(IPI_IMR, PL_1, 25, 1) 101 FIELD(IPI_IER, PL_1, 25, 1) 113 FIELD(IPI_IDR, PL_1, 25, 1) 135 int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27};`
/qemu/tests/tcg/i386/
H A D	float_convs.ref	68 from single: f32(0x1.00000000000000000000p-25:0x33000000) 69 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 74 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 75 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 255 from single: f32(0x1.00000000000000000000p-25:0x33000000) 256 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 261 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 262 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 442 from single: f32(0x1.00000000000000000000p-25:0x33000000) 443 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) [all …]
/qemu/tests/tcg/x86_64/
H A D	float_convs.ref	68 from single: f32(0x1.00000000000000000000p-25:0x33000000) 69 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 74 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 75 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 255 from single: f32(0x1.00000000000000000000p-25:0x33000000) 256 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) 261 from single: f32(0x1.ffffe600000000000000p-25:0x337ffff3) 262 to double: f64(0x1.ffffe600000000000000p-25:0x003e6ffffe60000000) (OK) 442 from single: f32(0x1.00000000000000000000p-25:0x33000000) 443 to double: f64(0x1.00000000000000000000p-25:0x003e60000000000000) (OK) [all …]
/qemu/linux-user/ppc/
H A D	vdso.S	`116 .cfi_offset 25, 25 * sizeof_reg 152 .cfi_offset 57, offsetof_mcontext_fregs + 25 * sizeof_freg 211 save_vreg 25`
/qemu/linux-user/hppa/
H A D	vdso.S	`81 .cfi_offset 25, offsetof_sigcontext_gr + 25 * 4 132 .cfi_offset 74, offsetof_sigcontext_fr + 25 * 8 133 .cfi_offset 75, offsetof_sigcontext_fr + 25 * 8 + 4`
/qemu/scripts/kvm/
H A D	vmxcap	`156 25: 'Use I/O bitmaps', 194 25: 'TSC scaling', 223 25: 'Clear IA32_RTIT_CTL', 269 (25,27): 'MSR-load/store count recommendation', 291 25: 'Single-context INVEPT',`

12 3 4 5 6 7 8 9 10 >>...21

Project(s)

Full Search
Definition
Symbol
File Path
History
Type