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/qemu/hw/audio/
H A Dgustate.h43 #define VSRegsEnd (VSRControl+VSRegs + 32*(16*2))
44 #define VSRFreq (2)
63 #define wVSRLoopStartHi (2)
77 #define DataRegLoByte3x4 (VSRVolRampControl+2)
79 #define DataRegHiByte3x5 (VSRVolRampControl+2 +1)
80 #define DMA_2xB (VSRVolRampControl+2+2)
81 #define IRQ_2xB (VSRVolRampControl+2+3)
83 #define RegCtrl_2xF (VSRVolRampControl+2+(16*2))
84 #define Jumper_2xB (VSRVolRampControl+2+(16*2)+1)
85 #define GUS42DMAStart (VSRVolRampControl+2+(16*2)+2)
[all …]
/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc25 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0)
26 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0)
27 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0)
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0)
29 XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0)
30 XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0)
31 XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0)
32 XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0)
33 XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0)
34 XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, 0, 0, 0, 0, 0, 0)
[all …]
/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc9 the Free Software Foundation; either version 2 of the License, or
22 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc,
24 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0,
26 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1,
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2,
30 XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3,
32 XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4,
34 XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5,
36 XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6,
38 XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7,
[all …]
/qemu/include/tcg/
H A Dtcg-opc.h37 DEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT)
43 DEF(add, 1, 2, 0, TCG_OPF_INT)
44 DEF(and, 1, 2, 0, TCG_OPF_INT)
45 DEF(andc, 1, 2, 0, TCG_OPF_INT)
49 DEF(clz, 1, 2, 0, TCG_OPF_INT)
51 DEF(ctz, 1, 2, 0, TCG_OPF_INT)
52 DEF(deposit, 1, 2, 2, TCG_OPF_INT)
53 DEF(divs, 1, 2, 0, TCG_OPF_INT)
54 DEF(divs2, 2, 3, 0, TCG_OPF_INT)
55 DEF(divu, 1, 2, 0, TCG_OPF_INT)
[all …]
/qemu/include/libdecnumber/
H A DdecDPD.h9 Software Foundation; either version 2, or (at your option) any later
67 const uint16_t BCD2DPD[2458]={ 0, 1, 2, 3, 4, 5, 6, 7,
262 const uint16_t DPD2BCD[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
347 const uint16_t BIN2DPD[1000]={ 0, 1, 2, 3, 4, 5, 6, 7,
430 const uint16_t DPD2BIN[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
776 '\0','0','0','0', '\1','0','0','1', '\1','0','0','2', '\1','0','0','3', '\1','0','0','4',
778 '\2','0','1','0', '\2','0','1','1', '\2','0','1','2', '\2','0','1','3', '\2','0','1','4',
779 '\2','0','1','5', '\2','0','1','6', '\2','0','1','7', '\2','0','1','8', '\2','0','1','9',
780 '\2','0','2','0', '\2','0','2','1', '\2','0','2','2', '\2','0','2','3', '\2','0','2','4',
781 '\2','0','2','5', '\2','0','2','6', '\2','0','2','7', '\2','0','2','8', '\2','0','2','9',
[all …]
/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
33 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
[all …]
/qemu/tests/unit/
H A Dtest-smp-parse.c152 /* config: -smp sockets=2
153 * expect: cpus=2,sockets=2,cores=1,threads=1,maxcpus=2 */
154 .config = SMP_CONFIG_GENERIC(F, 0, T, 2, F, 0, F, 0, F, 0),
155 .expect_prefer_sockets = CPU_TOPOLOGY_GENERIC(2, 2, 1, 1, 2),
156 .expect_prefer_cores = CPU_TOPOLOGY_GENERIC(2, 2, 1, 1, 2),
164 /* config: -smp threads=2
165 * expect: cpus=2,sockets=1,cores=1,threads=2,maxcpus=2 */
166 .config = SMP_CONFIG_GENERIC(F, 0, F, 0, F, 0, T, 2, F, 0),
167 .expect_prefer_sockets = CPU_TOPOLOGY_GENERIC(2, 1, 1, 2, 2),
168 .expect_prefer_cores = CPU_TOPOLOGY_GENERIC(2, 1, 1, 2, 2),
[all …]
H A Dtest-x86-topo.c46 g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), ==, 2); in test_topo_bits()
52 topo_info = (X86CPUTopoInfo) {1, 1, 1, 2}; in test_topo_bits()
55 g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2); in test_topo_bits()
57 g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2); in test_topo_bits()
69 topo_info = (X86CPUTopoInfo) {1, 1, 30, 2}; in test_topo_bits()
71 topo_info = (X86CPUTopoInfo) {1, 1, 31, 2}; in test_topo_bits()
73 topo_info = (X86CPUTopoInfo) {1, 1, 32, 2}; in test_topo_bits()
75 topo_info = (X86CPUTopoInfo) {1, 1, 33, 2}; in test_topo_bits()
78 topo_info = (X86CPUTopoInfo) {1, 6, 30, 2}; in test_topo_bits()
80 topo_info = (X86CPUTopoInfo) {1, 7, 30, 2}; in test_topo_bits()
[all …]
/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/bsd-user/freebsd/
H A Dos-syscall.c9 * the Free Software Foundation; either version 2 of the License, or
228 case TARGET_FREEBSD_NR_fork: /* fork(2) */ in freebsd_syscall()
232 case TARGET_FREEBSD_NR_vfork: /* vfork(2) */ in freebsd_syscall()
236 case TARGET_FREEBSD_NR_rfork: /* rfork(2) */ in freebsd_syscall()
240 case TARGET_FREEBSD_NR_pdfork: /* pdfork(2) */ in freebsd_syscall()
244 case TARGET_FREEBSD_NR_execve: /* execve(2) */ in freebsd_syscall()
248 case TARGET_FREEBSD_NR_fexecve: /* fexecve(2) */ in freebsd_syscall()
252 case TARGET_FREEBSD_NR_wait4: /* wait4(2) */ in freebsd_syscall()
256 case TARGET_FREEBSD_NR_wait6: /* wait6(2) */ in freebsd_syscall()
261 case TARGET_FREEBSD_NR_exit: /* exit(2) */ in freebsd_syscall()
[all …]
/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc5 F2(RI_a, R(1, 8), I(2,16,16))
6 F2(RI_b, R(1, 8), I(2,16,16))
7 F2(RI_c, M(1, 8), I(2,16,16))
8 F3(RIE_a, R(1, 8), I(2,16,16), M(3,32))
9 F4(RIE_b, R(1, 8), R(2,12), M(3,32), I(4,16,16))
10 F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
11 F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
12 F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
13 F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
14 F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
[all …]
/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/tests/qemu-iotests/
H A D013.out521 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
523 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
525 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
527 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
529 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
531 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
533 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
535 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
537 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
539 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D022.out521 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
523 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
525 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
527 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
529 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
531 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
533 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
535 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
537 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
539 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
H A D014.out519 === Clusters to be compressed [2]
2061 === Used clusters [2]
6172 === Clusters to be compressed [2]
7714 === Used clusters [2]
11826 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11828 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11830 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11832 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11834 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
11836 2 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
[all …]
/qemu/target/arm/tcg/
H A Dmve.decode29 # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit,
31 %2op_fp_size 20:1 !function=neon_3same_fp_size
33 %2op_fp_size_rev 20:1 !function=plus_1
35 %2op_fp_scalar_size 28:1 !function=neon_3same_fp_size
42 &2op qd qm qn size
43 &2scalar qd qn rm size
45 &2shift qd qm shift size
64 @vldst_sg .... .... .... rn:4 .... ... size:2 ... ... os:1 &vldst_sg \
72 @vldst_il .... .... .. w:1 . rn:4 .... ... size:2 pat:2 ..... &vldst_il \
75 @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm
[all …]
H A Dneon-dp.decode37 # 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
42 @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
45 @3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
100 @3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \
186 # 2-reg-and-shift grouping:
189 &2reg_shift vm vd q shift size
197 @2reg_shr_d .... ... . . . ...... .... .... 1 q:1 . . .... \
198 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
199 @2reg_shr_s .... ... . . . 1 ..... .... .... 0 q:1 . . .... \
200 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
[all …]
/qemu/disas/
H A Dsparc.c17 the Free Software Foundation; either version 2, or (at your option)
97 #define F_ALIAS 2 /* Alias for a "real" instruction. */
117 2 rs2 register.
142 k 2+14 bit PC relative immediate. (v9)
192 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
236 Software Foundation; either version 2, or (at your option) any later
357 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
358 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \
359 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask }
363 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 },
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_b.S13 j 2f
16 2:
27 j 2f
30 2:
45 j 2f
48 2:
59 j 2f
62 2:
65 j 2f
68 2:
[all …]
/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
33 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/qemu/hw/display/
H A Dxlnx_dp.c12 * the Free Software Foundation, either version 2 of the License, or
47 #define DP_LINK_BW_SET (0x0000 >> 2)
48 #define DP_LANE_COUNT_SET (0x0004 >> 2)
49 #define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
50 #define DP_TRAINING_PATTERN_SET (0x000C >> 2)
51 #define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
52 #define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
53 #define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
54 #define DP_SOFTWARE_RESET (0x001C >> 2)
55 #define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
[all …]
/qemu/hw/pci-host/
H A Dgt64120.c42 #define GT_REGS (0x1000 >> 2)
45 #define GT_CPU (0x000 >> 2)
46 #define GT_MULTI (0x120 >> 2)
52 #define GT_SCS10LD (0x008 >> 2)
53 #define GT_SCS10HD (0x010 >> 2)
54 #define GT_SCS32LD (0x018 >> 2)
55 #define GT_SCS32HD (0x020 >> 2)
56 #define GT_CS20LD (0x028 >> 2)
57 #define GT_CS20HD (0x030 >> 2)
58 #define GT_CS3BOOTLD (0x038 >> 2)
[all …]

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