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/linux-6.8/drivers/phy/marvell/
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
37 #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2)
85 #define MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN BIT(2)
108 /* Relative to priv->regmap */
111 #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */
129 * A lane is described by the following bitfields:
130 * [ 1- 0]: COMPHY polarity invertion
[all …]
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
69 #define SPEED_PLL_MASK GENMASK(7, 2)
138 #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
156 #define MODE_MARGIN_OVERRIDE BIT(2)
161 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
[all …]
Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
29 #define COMPHY_STAT1_PLL_RDY_RX BIT(2)
47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
59 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
61 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
64 if (priv->conf) { in a38x_set_conf()
65 conf = readl_relaxed(priv->conf); in a38x_set_conf()
67 conf |= BIT(lane->port); in a38x_set_conf()
69 conf &= ~BIT(lane->port); in a38x_set_conf()
70 writel(conf, priv->conf); in a38x_set_conf()
[all …]
/linux-6.8/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_training_fixed_vs_pe_retimer.c42 link->ctx->logger
52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust()
60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
[all …]
Dlink_dp_training.c52 link->ctx->logger
67 switch (lt_settings->link_settings.link_rate) { in dp_log_training_result()
152 switch (lt_settings->link_settings.link_spread) { in dp_log_training_result()
168 /* TODO - DP2.0 Log: add connectivity log for FFE PRESET */ in dp_log_training_result()
172 lt_settings->link_settings.lane_count, in dp_log_training_result()
174 lt_settings->hw_lane_settings[0].VOLTAGE_SWING, in dp_log_training_result()
175 lt_settings->hw_lane_settings[0].PRE_EMPHASIS, in dp_log_training_result()
261 nibble = buf[index / 2]; in dp_get_nibble_at_index()
263 if (index % 2) in dp_get_nibble_at_index()
305 uint32_t lane; in maximize_lane_settings() local
[all …]
/linux-6.8/Documentation/devicetree/bindings/usb/
Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
20 vcc-supply:
23 enable-gpios: true
25 retimer-switch:
29 orientation-switch:
[all …]
/linux-6.8/Documentation/devicetree/bindings/media/
Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
[all …]
/linux-6.8/drivers/gpu/drm/i915/display/
Dintel_cx0_phy_regs.h1 /* SPDX-License-Identifier: MIT
15 #define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
30 #define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
44 #define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
68 #define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
85 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
86 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
[all …]
Dintel_dp_link_training.c2 * Copyright © 2008-2015 Intel Corporation
30 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \
31 (_intel_dp)->attached_connector->base.name, \
32 dp_to_dig_port(_intel_dp)->base.base.base.id, \
33 dp_to_dig_port(_intel_dp)->base.base.name, \
37 drm_dbg_kms(&dp_to_i915(_intel_dp)->drm, \
42 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \
43 drm_err(&dp_to_i915(_intel_dp)->drm, \
52 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); in intel_dp_reset_lttpr_common_caps()
57 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - in intel_dp_reset_lttpr_count()
[all …]
/linux-6.8/Documentation/devicetree/bindings/media/i2c/
Dst,st-mipid02.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
[all …]
/linux-6.8/sound/soc/tegra/
Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
46 ASRC_STREAM_REG_DEFAULTS(2),
73 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
83 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
84 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
94 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
101 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
103 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
106 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
[all …]
/linux-6.8/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/linux-6.8/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
83 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
85 if (!dp->force_hpd) in analogix_dp_detect_hpd()
86 return -ETIMEDOUT; in analogix_dp_detect_hpd()
93 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
98 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
99 return -EINVAL; in analogix_dp_detect_hpd()
102 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
112 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
114 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
[all …]
/linux-6.8/drivers/phy/tegra/
Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
128 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
134 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2
158 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2)
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
[all …]
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
33 #define USB2_PORT_SHIFT(x) ((x) * 2)
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
80 #define USB2_OTG_PD_DR BIT(2)
140 #define UTMI_LS SPEED(2)
154 #define FAKE_USBOP_EN BIT(2)
[all …]
Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
66 USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \
68 SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \
75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
106 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
146 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
188 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
276 (((_port) <= 2) ? (_offset1) : (_offset2))
[all …]
/linux-6.8/drivers/thunderbolt/
Dlc.c1 // SPDX-License-Identifier: GPL-2.0
12 * tb_lc_read_uuid() - Read switch UUID from link controller common register
18 if (!sw->cap_lc) in tb_lc_read_uuid()
19 return -EINVAL; in tb_lc_read_uuid()
20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); in tb_lc_read_uuid()
25 if (!sw->cap_lc) in read_lc_desc()
26 return -EINVAL; in read_lc_desc()
27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); in read_lc_desc()
32 struct tb_switch *sw = port->sw; in find_port_lc_cap()
43 phys = tb_phy_port_from_link(port->port); in find_port_lc_cap()
[all …]
/linux-6.8/drivers/phy/freescale/
Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
12 #define LYNX_28G_NUM_PLL 2
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
51 #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
[all …]
/linux-6.8/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
46 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
137 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
138 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
[all …]
/linux-6.8/drivers/phy/rockchip/
Dphy-rockchip-typec.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
5 * Kever Yang <kever.yang@rock-chips.com>
7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
24 * 2. DP only mode:
34 * This Type-C PHY driver supports normal and flip orientation. The orientation
40 #include <linux/clk-provider.h>
58 #define CMN_SSM_BANDGAP (0x21 << 2)
59 #define CMN_SSM_BIAS (0x22 << 2)
[all …]
/linux-6.8/drivers/media/platform/ti/omap3isp/
Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
[all …]
/linux-6.8/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
[all …]
/linux-6.8/drivers/platform/x86/intel/pmc/
Dspt.c1 // SPDX-License-Identifier: GPL-2.0
22 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
23 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
24 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
25 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
26 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
27 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
28 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
29 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
30 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
[all …]
/linux-6.8/drivers/net/dsa/mv88e6xxx/
Dserdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
39 return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); in mv88e6390_serdes_read()
45 state->link = false; in mv88e6xxx_pcs_decode_state()
53 state->link = !!(status & MV88E6390_SGMII_PHY_STATUS_LINK); in mv88e6xxx_pcs_decode_state()
54 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); in mv88e6xxx_pcs_decode_state()
61 state->duplex = status & in mv88e6xxx_pcs_decode_state()
66 state->pause |= MLO_PAUSE_TX; in mv88e6xxx_pcs_decode_state()
68 state->pause |= MLO_PAUSE_RX; in mv88e6xxx_pcs_decode_state()
72 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) in mv88e6xxx_pcs_decode_state()
[all …]
/linux-6.8/Documentation/devicetree/bindings/phy/
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]

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