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/linux-5.10/Documentation/hwmon/
Dlochnagar.rst31 power1_average_interval Power averaging time input valid from 1 to 1708mS
33 in1_input Measured voltage for 1V8 DSP (milliVolts)
34 in1_label "1V8 DSP"
35 curr2_input Measured current for 1V8 DSP (milliAmps)
36 curr2_label "1V8 DSP"
37 power2_average Measured average power for 1V8 DSP (microWatts)
38 power2_average_interval Power averaging time input valid from 1 to 1708mS
39 power2_label "1V8 DSP"
40 in2_input Measured voltage for 1V8 CDC (milliVolts)
41 in2_label "1V8 CDC"
[all …]
/linux-5.10/arch/arm64/crypto/
Dsm4-ce-core.S6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8
19 ld1 {v8.4s}, [x2]
21 CPU_LE( rev32 v8.16b, v8.16b )
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
28 sm4e v8.4s, v5.4s
29 sm4e v8.4s, v6.4s
[all …]
Dsm3-ce-core.S11 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
44 sm3ss1 v5.4s, v8.4s, \t0\().4s, v9.4s
45 shl \t1\().4s, \t0\().4s, #1
47 sm3tt1\ab v8.4s, v5.4s, v10.4s, \i
62 round \ab, \s0, v12, v11, 1
78 ld1 {v8.4s-v9.4s}, [x0]
79 rev64 v8.4s, v8.4s
81 ext v8.16b, v8.16b, v8.16b, #8
89 sub w2, w2, #1
91 mov v15.16b, v8.16b
[all …]
Daes-neon.S24 tbnz \reg, #1, \lbl
30 shl \out, \in, #1
84 mul_by_x2 v8.16b, \in\().16b, v9.16b, v12.16b
85 eor \in\().16b, \in\().16b, v8.16b
86 rev32 v8.8h, v8.8h
87 eor \in\().16b, \in\().16b, v8.16b
90 mul_by_x v9.16b, \in\().16b, v8.16b, v12.16b
91 rev32 v8.8h, \in\().8h
92 eor v8.16b, v8.16b, v9.16b
93 eor \in\().16b, \in\().16b, v8.16b
[all …]
Dchacha-neon-core.S67 // x1 = shuffle32(x1, MASK(0, 3, 2, 1))
69 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
71 // x3 = shuffle32(x3, MASK(2, 1, 0, 3))
96 // x1 = shuffle32(x1, MASK(2, 1, 0, 3))
98 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
100 // x3 = shuffle32(x3, MASK(0, 3, 2, 1))
111 // x1: 1 data block output, o
112 // x2: 1 data block input, i
120 ld1 {v8.4s-v11.4s}, [x0]
127 add v0.4s, v0.4s, v8.4s
[all …]
Dsha3-ce-core.S3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
53 ld1 { v0.1d- v3.1d}, [x19]
54 ld1 { v4.1d- v7.1d}, [x8], #32
55 ld1 { v8.1d-v11.1d}, [x8], #32
56 ld1 {v12.1d-v15.1d}, [x8], #32
57 ld1 {v16.1d-v19.1d}, [x8], #32
58 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v24.1d}, [x8]
61 1: sub w21, w21, #1
[all …]
Daes-neonbs-core.S338 \t0, \t1, \t2, \t3, \t4, \t5, \t6, \t7, 1
359 swapmove_2x \x0, \x1, \x2, \x3, 1, \t0, \t2, \t3
360 swapmove_2x \x4, \x5, \x6, \x7, 1, \t0, \t2, \t3
385 ld1 {v17.4s}, [x1], #16 // load round 1 key
387 movi v8.16b, #0x01 // bit masks
397 sub x2, x2, #1
404 cmtst v0.16b, v7.16b, v8.16b
417 subs x2, x2, #1
438 tbl v0.16b, {v10.16b}, v8.16b
440 tbl v1.16b, {v11.16b}, v8.16b
[all …]
Dsha512-ce-core.S3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
117 0: ld1 {v8.2d-v11.2d}, [x19]
124 1: ld1 {v12.2d-v15.2d}, [x20], #64
126 sub w21, w21, #1
139 mov v0.16b, v8.16b
150 dround 0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17
151 dround 3, 0, 4, 2, 1, 21, 25, 13, 14, 12, 17, 18
152 dround 2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19
153 dround 4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12
[all …]
Daes-modes.S77 subs w4, w4, #1
108 subs w4, w4, #1
165 subs w4, w4, #1
197 ld1 {v4.16b}, [x1], #16 /* get 1 ct block */
205 ld1 {v5.16b}, [x1], #16 /* reload 1 ct block */
206 ld1 {cbciv.16b}, [x1], #16 /* reload 1 ct block */
218 ld1 {cbciv.16b}, [x1], #16 /* reload 1 ct block */
235 subs w4, w4, #1
334 umov x6, vctr.d[1] /* keep swabbed ctr in reg */
341 add w7, w6, #1
[all …]
Dsha1-ce-core.S3 * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
90 1: ld1 {v8.4s-v11.4s}, [x20], #64
91 sub w21, w21, #1
93 CPU_LE( rev32 v8.16b, v8.16b )
98 2: add t0.4s, v8.4s, k0.4s
138 b 1b
155 mov v11.d[1], x7
/linux-5.10/arch/sh/boards/mach-hp6xx/
Dsetup.c31 [1] = {
44 .id = -1,
51 .id = -1,
57 u8 v8; in dac_audio_start() local
65 v8 = inb(PKDR); in dac_audio_start()
66 v8 &= ~PKDR_SPEAKER; in dac_audio_start()
67 outb(v8, PKDR); in dac_audio_start()
75 u8 v8; in dac_audio_stop() local
83 v8 = inb(PKDR); in dac_audio_stop()
84 v8 |= PKDR_SPEAKER; in dac_audio_stop()
[all …]
/linux-5.10/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.txt51 - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
52 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
55 pinctrl-1.
56 - pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
59 using pads at 3V3 and 1V8 levels.
60 - nvidia,only-1-8-v : The presence of this property indicates that the
65 - nvidia,pad-autocal-pull-up-offset-1v8,
66 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
72 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
73 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
[all …]
/linux-5.10/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S101 vspltisw v0,-1
106 /* Get the initial value into v8 */
107 vxor v8,v8,v8
108 MTVRD(v8, R3)
110 vsldoi v8,zeroes,v8,8 /* shift into bottom 32 bits */
112 vsldoi v8,v8,zeroes,4 /* shift into top 32 bits */
129 1: lis r7,MAX_SIZE@h
150 addi r7,r7,-1
175 cmpdi r0,1
198 vxor v16,v16,v8
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight-cti.yaml32 are implementation defined, except when the CTI is connected to an ARM v8
35 In this case the ARM v8 architecture defines the required signal connections
36 between CTI and the CPU core and ETM if present. In the case of a v8
38 indicate this feature (arm,coresight-cti-v8-arch).
88 - const: arm,coresight-cti-v8-arch
93 maxItems: 1
99 base cti node if compatible string arm,coresight-cti-v8-arch is used,
115 compatible string arm,coresight-cti-v8-arch used. If the associated
126 const: 1
140 maxItems: 1
[all …]
/linux-5.10/arch/s390/kernel/
Dfpu.c32 asm volatile("std 1,%0" : "=Q" (state->fprs[1])); in __kernel_fpu_begin()
57 " la 1,%[vxrs]\n" /* load save area */ in __kernel_fpu_begin()
63 * case a vstm V8..V23 is the best instruction in __kernel_fpu_begin()
66 " jne 0f\n" /* -> save V8..V23 */ in __kernel_fpu_begin()
67 " VSTM 8,23,128,1\n" /* vstm %v8,%v23,128(%r1) */ in __kernel_fpu_begin()
73 " brc 2,1f\n" /* 10 -> save V8..V15 */ in __kernel_fpu_begin()
74 " VSTM 0,7,0,1\n" /* vstm %v0,%v7,0(%r1) */ in __kernel_fpu_begin()
76 "1: VSTM 8,15,128,1\n" /* vstm %v8,%v15,128(%r1) */ in __kernel_fpu_begin()
78 "2: VSTM 0,15,0,1\n" /* vstm %v0,%v15,0(%r1) */ in __kernel_fpu_begin()
84 " VSTM 16,23,256,1\n" /* vstm %v16,%v23,256(%r1) */ in __kernel_fpu_begin()
[all …]
/linux-5.10/arch/arm64/boot/dts/arm/
DMakefile3 foundation-v8.dtb foundation-v8-psci.dtb \
4 foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
7 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
/linux-5.10/tools/testing/selftests/powerpc/copyloops/
Dmemcpy_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
42 bf cr7*4+3,1f
44 addi r4,r4,1
46 addi r3,r3,1
48 1: bf cr7*4+2,2f
54 2: bf cr7*4+1,3f
136 6: bf cr7*4+1,7f
191 12: bf cr7*4+1,13f
232 * 1 for the store side.
236 ori r9,r9,1 /* stream=1 */
[all …]
Dcopyuser_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
98 bf cr7*4+3,1f
100 addi r4,r4,1
102 addi r3,r3,1
104 1: bf cr7*4+2,2f
110 2: bf cr7*4+1,3f
192 6: bf cr7*4+1,7f
247 12: bf cr7*4+1,13f
286 * 1 for the store side.
290 ori r9,r9,1 /* stream=1 */
[all …]
/linux-5.10/arch/powerpc/lib/
Dmemcpy_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
42 bf cr7*4+3,1f
44 addi r4,r4,1
46 addi r3,r3,1
48 1: bf cr7*4+2,2f
54 2: bf cr7*4+1,3f
136 6: bf cr7*4+1,7f
191 12: bf cr7*4+1,13f
232 * 1 for the store side.
236 ori r9,r9,1 /* stream=1 */
[all …]
Dcopyuser_power7.S11 /* 0 == don't use VMX, 1 == use VMX */
98 bf cr7*4+3,1f
100 addi r4,r4,1
102 addi r3,r3,1
104 1: bf cr7*4+2,2f
110 2: bf cr7*4+1,3f
192 6: bf cr7*4+1,7f
247 12: bf cr7*4+1,13f
286 * 1 for the store side.
290 ori r9,r9,1 /* stream=1 */
[all …]
/linux-5.10/arch/sparc/math-emu/
Dmath_32.c31 * These are defined in the third layer of macros: op-1.h, op-2.h
33 * of 1,2 and 4 machine words respectively. [For example, on sparc64
35 * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
47 * SPARC architecture manual V9, and what I really want is V8...
50 * has to be emulated on V8). So I think I'm going to have
86 #define FSQRTQ 0x02b /* v8 */
87 #define FADDQ 0x043 /* v8 */
88 #define FSUBQ 0x047 /* v8 */
89 #define FMULQ 0x04b /* v8 */
90 #define FDIVQ 0x04f /* v8 */
[all …]
/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h64 REG_SET_N(reg_name, 1, initial_val, \
116 f5, v5, f6, v6, f7, v7, f8, v8) \ argument
125 FN(reg, f8), v8)
128 v5, f6, v6, f7, v7, f8, v8, f9, v9) \ argument
137 FN(reg, f8), v8, \
141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ argument
150 FN(reg, f8), v8, \
205 #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ argument
214 FN(reg_name, f8), v8)
231 REG_UPDATE_N(reg_name, 1, \
[all …]
/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi6220-coresight.dtsi78 #address-cells = <1>;
89 port@1 {
90 reg = <1>;
147 #address-cells = <1>;
158 port@1 {
159 reg = <1>;
380 compatible = "arm,coresight-cti-v8-arch",
391 /* CTI - CPU-1 */
393 compatible = "arm,coresight-cti-v8-arch",
406 compatible = "arm,coresight-cti-v8-arch",
[all …]
/linux-5.10/arch/s390/crypto/
Dcrc32le-vx.S38 * R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
39 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
40 * R3 = [(x128+32 mod P'(x) << 32)]' << 1
41 * R4 = [(x128-32 mod P'(x) << 32)]' << 1
42 * R5 = [(x64 mod P'(x) << 32)]' << 1
43 * R6 = [(x32 mod P'(x) << 32)]' << 1
68 .octa 0x1DB710641 # P'(x) << 1
76 .octa 0x105ec76f0 # P'(x) << 1
99 * V5..V8: Next data chunks that are fetched from the input buffer.
144 /* Load the next 64-byte data chunk into V5 to V8 */
[all …]
/linux-5.10/drivers/hwtracing/coresight/
Dcoresight-cti-platform.c17 /* Number of CTI signals in the v8 architecturally defined connection */
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
48 return -1; in of_cti_get_cpu_at_node()
53 return -1; in of_cti_get_cpu_at_node()
58 return (cpu < 0) ? -1 : cpu; in of_cti_get_cpu_at_node()
64 return -1; in of_cti_get_cpu_at_node()
78 return -1; in cti_plat_get_cpu_at_node()
170 * Create an architecturally defined v8 connection
186 "ARM v8 architectural CTI connection: missing cpu\n"); in cti_plat_create_v8_connections()
191 /* Allocate the v8 cpu connection memory */ in cti_plat_create_v8_connections()
[all …]

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