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/linux-6.15/arch/x86/crypto/
Dsha512-avx2-asm.S184 rorx $18, e, y1 # y1 = e >> 18 # S1B
185 add frame_XFER(%rsp),h # h = k + w + h # --
190 xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
195 xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
197 add h, d # d = k + w + h + d # --
210 add y1, h # h = k + w + h + S0 # --
212 add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
214 add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
234 # Move to appropriate lanes for calculating w[18] and w[19]
246 rorx $18, e, y1 # y1 = e >> 18 # S1B
[all …]
Dsha512-avx-asm.S78 # W[t] + K[t] | W[t+1] + K[t+1]
101 # W[t]+K[t] (stack frame)
132 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
133 RORQ tmp0, 4 # 18 # tmp = ((e ror 23) ^ e) ror 4
136 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
138 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
160 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
161 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
190 RORQ tmp0, 4 # 18
239 RORQ tmp0, 4 # 18
[all …]
/linux-6.15/crypto/
Dserpent_generic.c25 ({ b ^= d; b ^= c; b ^= a; b ^= PHI ^ i; b = rol32(b, 11); k[j] = b; })
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
36 #define K(x0, x1, x2, x3, i) ({ \ macro
37 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
38 x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \
48 x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \
49 x1 ^= k[4*i+1]; x0 = rol32(x0, 5); x2 = rol32(x2, 22);\
50 x0 ^= k[4*i+0]; x2 ^= k[4*i+2]; \
54 x0 ^= k[4*i+0]; x1 ^= k[4*i+1]; x2 ^= k[4*i+2]; \
[all …]
Dsm3.c15 static const u32 ____cacheline_aligned K[64] = { variable
85 R1(a, b, c, d, e, f, g, h, K[0], I(0), I(4)); in sm3_transform()
86 R1(d, a, b, c, h, e, f, g, K[1], I(1), I(5)); in sm3_transform()
87 R1(c, d, a, b, g, h, e, f, K[2], I(2), I(6)); in sm3_transform()
88 R1(b, c, d, a, f, g, h, e, K[3], I(3), I(7)); in sm3_transform()
89 R1(a, b, c, d, e, f, g, h, K[4], W1(4), I(8)); in sm3_transform()
90 R1(d, a, b, c, h, e, f, g, K[5], W1(5), I(9)); in sm3_transform()
91 R1(c, d, a, b, g, h, e, f, K[6], W1(6), I(10)); in sm3_transform()
92 R1(b, c, d, a, f, g, h, e, K[7], W1(7), I(11)); in sm3_transform()
93 R1(a, b, c, d, e, f, g, h, K[8], W1(8), I(12)); in sm3_transform()
[all …]
/linux-6.15/tools/testing/selftests/bpf/progs/
Dfexit_many_args.c14 test1_result = a == 16 && b == (void *)17 && c == 18 && d == 19 && in BPF_PROG()
22 int g, unsigned int h, long i, __u64 j, unsigned long k, in BPF_PROG() argument
25 test2_result = a == 16 && b == (void *)17 && c == 18 && d == 19 && in BPF_PROG()
27 i == 24 && j == 25 && k == 26 && ret == 231; in BPF_PROG()
34 __u64 g, __u64 h, __u64 i, __u64 j, __u64 k, __u64 ret) in BPF_PROG() argument
36 test3_result = a == 16 && b == 17 && c == 18 && d == 19 && in BPF_PROG()
38 i == 24 && j == 25 && k == 26 && ret == 231; in BPF_PROG()
Dfentry_many_args.c14 test1_result = a == 16 && b == (void *)17 && c == 18 && d == 19 && in BPF_PROG()
22 int g, unsigned int h, long i, __u64 j, unsigned long k) in BPF_PROG() argument
24 test2_result = a == 16 && b == (void *)17 && c == 18 && d == 19 && in BPF_PROG()
26 i == 24 && j == 25 && k == 26; in BPF_PROG()
33 __u64 g, __u64 h, __u64 i, __u64 j, __u64 k) in BPF_PROG() argument
35 test3_result = a == 16 && b == 17 && c == 18 && d == 19 && in BPF_PROG()
37 i == 24 && j == 25 && k == 26; in BPF_PROG()
/linux-6.15/include/uapi/linux/
Dkeyboard.h45 #define K(t,v) (((t)<<8)|(v)) macro
49 #define K_F1 K(KT_FN,0)
50 #define K_F2 K(KT_FN,1)
51 #define K_F3 K(KT_FN,2)
52 #define K_F4 K(KT_FN,3)
53 #define K_F5 K(KT_FN,4)
54 #define K_F6 K(KT_FN,5)
55 #define K_F7 K(KT_FN,6)
56 #define K_F8 K(KT_FN,7)
57 #define K_F9 K(KT_FN,8)
[all …]
/linux-6.15/arch/sparc/crypto/
Dcamellia_asm.S36 ld [%o0 + 0x00], %f0 ! i0, k[0]
37 ld [%o0 + 0x04], %f1 ! i1, k[1]
38 ld [%o0 + 0x08], %f2 ! i2, k[2]
39 ld [%o0 + 0x0c], %f3 ! i3, k[3]
40 std %f0, [%o1 + 0x00] ! k[0, 1]
42 std %f2, [%o1 + 0x08] ! k[2, 3]
49 std %f0, [%o1 + 0x20] ! k[8, 9]
57 std %f2, [%o1 + 0x28] ! k[10, 11]
71 CAMELLIA_F(18, 0, 2, 0)
89 std %f0, [%o1 + 0x10] ! k[ 4, 5]
[all …]
/linux-6.15/arch/powerpc/crypto/
Dmd5-asm.S68 addi w0,w0,k0l; /* 1: wk = w + k */ \
70 addis w0,w0,k0h; /* 1: wk = w + k' */ \
71 addis w1,w1,k1h; /* 2: wk = w + k */ \
73 addi w1,w1,k1l; /* 2: wk = w + k' */ \
88 addi w0,w0,k0l; /* 1: wk = w + k */ \
90 addis w0,w0,k0h; /* 1: wk = w + k' */ \
92 addi w1,w1,k1l; /* 2: wk = w + k */ \
94 addis w1,w1,k1h; /* 2: wk = w + k' */ \
107 addi w0,w0,k0l; /* 1: wk = w + k */ \
109 addis w0,w0,k0h; /* 1: wk = w + k' */ \
[all …]
Dpoly1305-p10le_64.S49 # poly1305_p10le_4blocks( uint8_t *k, uint32_t mlen, uint8_t *m)
50 # k = 32 bytes key
51 # r3 = k (r, s)
101 SAVE_GPR 18, 144, 1
134 SAVE_VSX 18, 256, 9
169 RESTORE_VSX 18, 256, 9
188 RESTORE_GPR 18, 144, 1
256 vmulouw 18, 4, 30
259 vaddudm 18, 18, 10
260 vaddudm 18, 18, 11
[all …]
/linux-6.15/Documentation/devicetree/bindings/
Dtrivial-devices.yaml228 # Microchip differential I2C ADC, 1 Channel, 18 bit
230 # Microchip differential I2C ADC, 2 Channel, 18 bit
232 # Microchip differential I2C ADC, 2 Channel, 18 bit
234 # Microchip differential I2C ADC, 4 Channel, 18 bit
244 # Microchip 7-bit Single I2C Digital POT (10k)
246 # Microchip 7-bit Single I2C Digital POT (100k)
248 # Microchip 7-bit Single I2C Digital POT (5k)
250 # Microchip 7-bit Single I2C Digital POT (50k)
252 # Microchip 7-bit Single I2C Digital POT (10k)
254 # Microchip 7-bit Single I2C Digital POT (100k)
[all …]
/linux-6.15/tools/testing/kunit/test_data/
Dtest_output_isolated_correctly.log1 …@mactruck.svl.corp.google.com) (gcc version 7.3.0 (Debian 7.3.0-18)) #163 Wed May 8 16:18:20 PDT 2…
6 Memory: 254468K/283500K available (1734K kernel code, 489K rwdata, 396K rodata, 85K init, 216K bss,…
/linux-6.15/arch/arc/include/asm/
Duaccess.h11 * -stock kernel shrunk by 33K at -O3
15 * -kernel shrunk by 200K even at -O3 (gcc 4.2.1)
28 #define __get_user_fn(sz, u, k) \ argument
32 case 1: __arc_get_user_one(*(k), u, "ldb", __ret); break; \
33 case 2: __arc_get_user_one(*(k), u, "ldw", __ret); break; \
34 case 4: __arc_get_user_one(*(k), u, "ld", __ret); break; \
35 case 8: __arc_get_user_one_64(*(k), u, __ret); break; \
89 #define __put_user_fn(sz, u, k) \ argument
93 case 1: __arc_put_user_one(*(k), u, "stb", __ret); break; \
94 case 2: __arc_put_user_one(*(k), u, "stw", __ret); break; \
[all …]
/linux-6.15/drivers/media/i2c/
Dmt9t112.c305 dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable); in mt9t112_clock_info()
309 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable); in mt9t112_clock_info()
313 dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable); in mt9t112_clock_info()
317 dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable); in mt9t112_clock_info()
321 dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable); in mt9t112_clock_info()
325 dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable); in mt9t112_clock_info()
329 dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable); in mt9t112_clock_info()
332 dev_dbg(&client->dev, "External sensor : %10u K\n", clk); in mt9t112_clock_info()
336 dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable); in mt9t112_clock_info()
354 mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width); in mt9t112_set_a_frame_size()
[all …]
/linux-6.15/drivers/clk/berlin/
Dbg2q.c129 BERLIN2_PLL_SELECT(REG_CLKSELECT0, 18),
161 BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18),
204 BERLIN2_PLL_SELECT(REG_CLKSELECT1, 18),
276 { "nfc", "perif", 18 },
340 int k; in berlin2q_clock_setup() local
342 for (k = 0; k < dd->num_parents; k++) in berlin2q_clock_setup()
343 parent_names[k] = clk_names[dd->parent_ids[k]]; in berlin2q_clock_setup()
/linux-6.15/Documentation/devicetree/bindings/arm/marvell/
Dap80x-system-controller.txt5 7K/8K/931x SoCs. It contains system controllers, which provide several
69 mpp18 18 gpio
79 - compatible: "marvell,armada-8k-gpio"
103 compatible = "marvell,armada-8k-gpio";
136 - interrupts: overheat interrupt handle. Should point to line 18 of the
152 interrupts = <18>;
/linux-6.15/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi63 compatible = "marvell,armada-7k-pp22";
67 <&CP11X_LABEL(clk) 1 18>;
140 <&CP11X_LABEL(clk) 1 18>;
182 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
192 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
220 compatible = "marvell,armada-8k-rtc";
236 compatible = "marvell,armada-8k-gpio";
257 compatible = "marvell,armada-8k-gpio";
313 compatible = "marvell,armada-8k-xhci",
325 compatible = "marvell,armada-8k-xhci",
[all …]
/linux-6.15/Documentation/devicetree/bindings/phy/
Dphy-mvebu-comphy.txt5 * Armada 7k/8k (on the CP110)
13 * "marvell,comphy-cp110" for Armada 7k/8k
16 * 1 entry for Armada 7k/8k
24 controller node (only for Armada 7k/8k)
50 <&CP11X_LABEL(clk) 1 18>;
/linux-6.15/drivers/gpu/drm/imagination/
Dpvr_rogue_cr_defs_client.h67 #define ROGUE_CR_TE_MTILE1_X1_SHIFT 18
88 #define ROGUE_CR_TE_MTILE2_Y1_SHIFT 18
129 * Screen height in pixels. (16K x 16K max screen size)
134 * Screen width in pixels.(16K x 16K max screen size)
/linux-6.15/arch/powerpc/
DKconfig39 # consume "normal" amounts of address space. Book3S 64 only supports 64K
40 # and 4K page sizes.
41 default 29 if PPC_BOOK3S_64 && PPC_64K_PAGES # 29 = 45 (32T) - 16 (64K)
42 default 33 if PPC_BOOK3S_64 # 33 = 45 (32T) - 12 (4K)
46 # of address space (2^44). Only 4K page sizes are supported.
47 default 32 if 64BIT # 32 = 44 (16T) - 12 (4K)
54 default 14 if 64BIT && PPC_64K_PAGES # 14 = 30 (1GB) - 16 (64K)
55 default 18 if 64BIT # 18 = 30 (1GB) - 12 (4K)
63 default 11 if PPC_256K_PAGES # 11 = 29 (512MB) - 18 (256K)
64 default 13 if PPC_64K_PAGES # 13 = 29 (512MB) - 16 (64K)
[all …]
/linux-6.15/arch/m68k/include/asm/
Dthread_info.h9 * On machines with 4k pages we default to an 8k thread size, though we
10 * allow a 4k with config option. Any other machine page size then
11 * the thread size must match the page size (which is 8k and larger here).
69 #define TIF_RESTORE_SIGMASK 18 /* restore signal mask in do_signal */
/linux-6.15/drivers/scsi/
Dfdomain.c12 * TMC-1800, TMC-18C50, TMC-18C30, TMC-36C70
43 * More recently, boards are being produced with the TMC-18C50 and TMC-18C30
56 * "Technical Reference Manual: 18C50 SCSI Host Adapter Chip", Future Domain
73 * TMC-18C30 detection.)
78 * "18C30 Technical Reference Manual", Future Domain Corporation, 1993, page
94 * FIFO_COUNT: The host adapter has an 8K cache (host adapters based on the
95 * 18C30 chip have a 2k cache). When this many 512 byte blocks are filled by
142 case 0x60e9: /* 18c50 or 18c30 */ in fdomain_identify()
148 /* Try to toggle 32-bit mode. This only works on an 18c30 chip. */ in fdomain_identify()
155 /* If that failed, we are an 18c50. */ in fdomain_identify()
[all …]
/linux-6.15/drivers/i3c/master/mipi-i3c-hci/
Dhci_quirks.c7 * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
33 data |= W0_MASK(18, 16); in amd_set_od_pp_timing()
/linux-6.15/drivers/gpu/drm/
Ddrm_panic_qr.rs41 const P18: [u8; 18] = [
114 VersionParameter(&P30, 4, 18, 122), // V38
125 &[6, 18],
270 83, 166, 81, 162, 89, 178, 121, 242, 249, 239, 195, 155, 43, 86, 172, 69, 138, 9, 18, 36, 72,
279 218, 240, 18, 130, 69, 29, 181, 194, 125, 106, 39, 249, 185, 201, 154, 9, 120, 77, 228, 114,
657 for k in 0..size { in draw_square()
658 self.set(x + k, y); in draw_square()
659 self.set(x, y + k + 1); in draw_square()
660 self.set(x + size, y + k); in draw_square()
661 self.set(x + k + 1, y + size); in draw_square()
[all …]
/linux-6.15/arch/arm64/crypto/
Dsm3-neon-core.S121 #define R(i, a, b, c, d, e, f, g, h, k, K_LOAD, round, widx, wtype, IOP, iop_param) \ argument
128 add k, k, e; \
133 add k, k, t0; \
137 rolw(k, k, 7); /* rol (t0 + e + t), 7) => k */ \
139 add h, h, k; /* h + w1 + k => h */ \
142 eor t0, t0, k; /* k ^ t0 => t0 */ \
155 #define R1(a, b, c, d, e, f, g, h, k, K_LOAD, round, widx, wtype, IOP, iop_param) \ argument
156 R(1, ##a, ##b, ##c, ##d, ##e, ##f, ##g, ##h, ##k, K_LOAD, round, widx, wtype, IOP, iop_param)
158 #define R2(a, b, c, d, e, f, g, h, k, K_LOAD, round, widx, wtype, IOP, iop_param) \ argument
159 R(2, ##a, ##b, ##c, ##d, ##e, ##f, ##g, ##h, ##k, K_LOAD, round, widx, wtype, IOP, iop_param)
[all …]

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