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/linux-6.8/arch/parisc/kernel/
Dhardware.c91 {HPHW_NPROC,0x501,0x4,0x81,"Merlin L2 132 (9000/778/B132L)"},
93 {HPHW_NPROC,0x503,0x4,0x81,"Merlin L2+ 132 (9000/778/B132L)"},
95 {HPHW_NPROC,0x505,0x4,0x81,"Raven L2 132 (9000/778/C132L)"},
99 {HPHW_NPROC,0x509,0x4,0x81,"712/132 L2 Upgrade"},
101 {HPHW_NPROC,0x50B,0x4,0x81,"715/132 L2 Upgrade"},
105 {HPHW_NPROC,0x50F,0x4,0x81,"Anole L2 132 (744)"},
107 {HPHW_NPROC,0x511,0x4,0x81,"Kiji L2 132"},
108 {HPHW_NPROC,0x512,0x4,0x81,"UL L2 132 (803/D220,D320)"},
110 {HPHW_NPROC,0x514,0x4,0x81,"Merlin Jr L2 132"},
111 {HPHW_NPROC,0x515,0x4,0x81,"Staccato L2 132"},
[all …]
/linux-6.8/drivers/gpu/drm/amd/display/dc/link/
Dlink_resource.c66 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability in link_get_cur_res_map()
85 /* remove excess 128b/132b encoding support for not recycled links */ in link_restore_res_map()
94 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */ in link_restore_res_map()
99 /* remove excess 128b/132b encoding support for recycled links */ in link_restore_res_map()
108 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */ in link_restore_res_map()
/linux-6.8/arch/arm64/boot/dts/ti/
Dk3-am62-wakeup.dtsi59 clocks = <&k3_clks 132 0>;
60 power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
61 assigned-clocks = <&k3_clks 132 0>;
62 assigned-clock-parents = <&k3_clks 132 2>;
Dk3-am62a-wakeup.dtsi58 clocks = <&k3_clks 132 0>;
59 power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
60 assigned-clocks = <&k3_clks 132 0>;
61 assigned-clock-parents = <&k3_clks 132 2>;
Dk3-am62p-wakeup.dtsi58 clocks = <&k3_clks 132 0>;
59 power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
60 assigned-clocks = <&k3_clks 132 0>;
61 assigned-clock-parents = <&k3_clks 132 2>;
/linux-6.8/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c320 /* 128b/132b */
424 "128b/132b, lanes: %d, " in intel_dp_get_adjust_train()
536 "128b/132b, lanes: %d, " in intel_dp_set_signal_levels()
583 /* 128b/132b */
724 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate in intel_dp_prepare_link_train()
863 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
874 /* UHBR+ use separate 128b/132b TPS2 */ in intel_dp_training_pattern()
1046 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); in intel_dp_stop_link_train()
1128 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1)
1141 * Reset signal levels. Start transmitting 128b/132b TPS1. in intel_dp_128b132b_lane_eq()
[all …]
/linux-6.8/drivers/media/platform/verisilicon/
Drockchip_av1_filmgrain.c60 -784, -280, 348, 108, -752, -132, 524, -540, -776, 116, -296,
68 -224, 596, -132, 268, 32, -452, 884, 104, -1008, 424, -1348,
76 -196, 604, 340, 384, 196, 592, -44, -500, 432, -580, -132,
82 -140, 48, -48, -60, 84, 72, 40, 132, -356, -268, -104,
86 472, 460, -232, 704, 120, 832, -228, 692, -508, 132, -476,
94 -692, -944, -620, 740, -240, 400, 132, 20, 192, -196, 264,
99 320, -8, -64, 156, -1016, 1084, 1172, 536, 484, -432, 132,
103 436, 896, 88, -392, 132, 80, -964, -288, 568, 56, -48,
110 -600, 768, 268, -248, -88, -132, -420, -432, 80, -288, 404,
123 -480, -628, -84, 192, 852, -404, -288, -132, 204, 100, 168,
[all …]
/linux-6.8/Documentation/driver-api/tty/
Dmoxa-smartio.rst27 CP-132U-I, CP-132UL,
28 CP-132, CP-132I, CP132S, CP-132IS,
/linux-6.8/drivers/video/fbdev/i810/
Di810_gtf.c38 { 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
52 { 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
66 { 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
79 { 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
93 { 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
107 { 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
/linux-6.8/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_training_128b_132b.c27 * This file implements dp 128b/132b link training software policies and
65 /* (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) * in dpcd_128b_132b_get_aux_rd_interval()
85 /* Transmit 128b/132b_TPS1 over Main-Link */ in dp_perform_128b_132b_channel_eq_done_sequence()
91 /* Adjust TX_FFE_PRESET_VALUE and Transmit 128b/132b_TPS2 over Main-Link */ in dp_perform_128b_132b_channel_eq_done_sequence()
/linux-6.8/drivers/gpu/drm/tidss/
Dtidss_scale_coefs.c18 .c1 = { 132, 138, 144, 150, 156, 162, 168, 174, 76, 84, 92, 98, 104, 110, 116, 124, },
24 .c1 = { 132, 138, 144, 152, 160, 166, 172, 178, 72, 80, 88, 94, 100, 108, 116, 124, },
30 .c1 = { 132, 140, 148, 156, 164, 172, 180, 186, 64, 72, 80, 88, 96, 104, 112, 122, },
84 .c1 = { 0, 28, 56, 94, 132, 176, 220, 266, -56, -60, -64, -62, -60, -50, -40, -20, },
104 .c1 = { 96, 80, 64, 50, 36, 26, 16, 136, 256, 236, 216, 194, 172, 152, 132, 114, },
114 .c1 = { 80, 64, 48, 36, 24, 16, 8, 132, 256, 232, 208, 186, 164, 142, 120, 100, },
/linux-6.8/drivers/pinctrl/mediatek/
Dpinctrl-mt8127.c128 MTK_PIN_DRV_GRP(132, 0xc10, 0, 2),
165 MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */
199 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
244 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
Dpinctrl-mt8183.c107 PIN_FIELD_BASE(132, 132, 8, 0x000, 0x10, 1, 1),
192 PIN_FIELD_BASE(132, 132, 8, 0x010, 0x10, 1, 1),
331 PIN_FIELD_BASE(132, 132, 8, 0x0A0, 0x10, 4, 3),
381 PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 10, 1),
426 PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 8, 1),
471 PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 9, 1),
/linux-6.8/Documentation/admin-guide/
Dsvga.rst128 (Usually 940=80x43, 941=132x25, 942=132x44, 943=80x60, 944=100x60,
129 945=132x28 for the standard Video7 BIOS)
145 E.g., 0x1950 corresponds to a 80x25 mode, 0x2b84 to 132x43 etc.
221 Added a Tseng 132x60 mode.
/linux-6.8/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/
Dia_css_ctc_table.host.c48 132, 132, 131, 130, 131, 130, 129, 128,
/linux-6.8/include/linux/
Ddio.h19 * range from 0-63 (DIO) and 132-255 (DIO-II).
27 * DIO-II boards are at 0x1000000 + (sc - 132) * 0x400000
119 #define DIOII_SCBASE 132 /* lowest DIO-II select code */
121 #define DIO_ISDIOII(scode) ((scode) >= 132 && (scode) < 256)
/linux-6.8/arch/powerpc/boot/dts/
Dmedia5200.dts30 bus-frequency = <132000000>; // 132 MHz
40 bus-frequency = <132000000>;// 132 MHz
/linux-6.8/include/uapi/linux/
Diso_fs.h41 __u8 logical_block_size [ISODCL (129, 132)]; /* 723 */
78 __u8 logical_block_size [ISODCL (129, 132)]; /* 723 */
125 __u8 volume_set_size [ISODCL (129, 132)]; /* 723 */
/linux-6.8/drivers/ata/pata_parport/
Daten.c7 * modes only. There is also an EH-132 which supports EPP mode
8 * transfers. The EH-132 is not yet supported.
/linux-6.8/include/dt-bindings/clock/
Drk3228-cru.h55 #define SCLK_MAC_OUT 132
278 #define SRST_TIMER2 132
/linux-6.8/drivers/pinctrl/uniphier/
Dpinctrl-uniphier-ld11.c357 UNIPHIER_PINCTRL_PIN(132, "HS1DIN5", UNIPHIER_PIN_IECTRL_EXIST,
358 132, UNIPHIER_PIN_DRV_1BIT,
359 132, UNIPHIER_PIN_PULL_DOWN),
500 132, 133, 134};
583 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */
710 if (gpio_offset == 132 || gpio_offset == 135) /* XIRQ12, 15 */ in uniphier_ld11_get_gpio_muxval()
/linux-6.8/tools/arch/x86/include/uapi/asm/
Dunistd_32.h12 #define __NR_getpgid 132
/linux-6.8/Documentation/devicetree/bindings/display/
Dsolomon,ssd1307fb.yaml135 default: 132
153 default: 132
/linux-6.8/arch/sh/include/mach-dreamcast/mach/
Ddma.h22 #define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132)
/linux-6.8/include/crypto/
Dserpent.h14 #define SERPENT_EXPKEY_WORDS 132

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