Home
last modified time | relevance | path

Searched full:13 (Results 1 – 25 of 852) sorted by relevance

12345678910>>...35

/qemu/net/can/
H A Dcan_core.c52 10, 10, 10, 10, /* 13 - 16 */
55 13, 13, 13, 13, 13, 13, 13, 13, /* 25 - 32 */
/qemu/include/hw/net/
H A Dmii.h36 #define MII_MDDACR 13 /* MMD access control */
48 #define MII_BMCR_SPEED100 (1 << 13) /* LSB of Speed (100) */
60 #define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */
74 #define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
97 #define MII_ANNP_MP (1 << 13) /* Message Page */
104 #define MII_STAT1000_LOK (1 << 13) /* Local Receiver Status */
109 #define MII_EXTSTAT_1000T_FD (1 << 13) /* 1000BASE-T Full Duplex */
H A Dnpcm_gmac.h54 #define RX_DESC_RDES0_SRC_ADDR_FILT_FAIL_MASK BIT(13)
116 #define TX_DESC_TDES0_FRM_FLSHD_MASK BIT(13)
213 #define NPCM_DMA_STATUS_FBI BIT(13)
260 #define NPCM_DMA_INTR_ENAB_FBE BIT(13)
307 #define NPCM_DMA_CONTROL_START_STOP_TX BIT(13)
/qemu/target/loongarch/
H A Dcpu-csr.h37 FIELD(CSR_ECFG, LIE, 0, 13)
41 FIELD(CSR_ESTAT, IS, 0, 13)
60 FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
61 FIELD(CSR_TLBEHI_64, VPPN, 13, 35)
72 FIELD(TLBENTRY, LEVEL, 13, 2)
171 FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
172 FIELD(CSR_TLBREHI_64, VPPN, 13, 35)
/qemu/tests/qtest/libqos/
H A Dvirtio-9p-client.c407 /* size[4] Rattach tag[2] qid[13] */
412 v9fs_memread(req, qid, 13); in v9fs_rattach()
475 /* size[4] Rwalk tag[2] nwqid[2] nwqid*(wqid[13]) */
486 *wqid = g_malloc(local_nwqid * 13); in v9fs_rwalk()
487 v9fs_memread(req, *wqid, local_nwqid * 13); in v9fs_rwalk()
526 * size[4] Rgetattr tag[2] valid[8] qid[13] mode[4] uid[4] gid[4] nlink[8]
537 v9fs_memread(req, &attr->qid, 13); in v9fs_rgetattr()
660 togo >= 13 + 8 + 1 + 2; in v9fs_rreaddir()
661 togo -= 13 + 8 + 1 + 2 + slen, ++n) in v9fs_rreaddir()
674 /* qid[13] offset[8] type[1] name[s] */ in v9fs_rreaddir()
[all …]
/qemu/linux-user/xtensa/
H A Dcpu_loop.c92 put_user_ual(env->regs[0], env->regs[13] - 16); in xtensa_overflow12()
94 put_user_ual(env->regs[1], env->regs[13] - 12); in xtensa_overflow12()
95 put_user_ual(env->regs[2], env->regs[13] - 8); in xtensa_overflow12()
96 put_user_ual(env->regs[3], env->regs[13] - 4); in xtensa_overflow12()
110 get_user_ual(env->regs[0], env->regs[13] - 16); in xtensa_underflow12()
111 get_user_ual(env->regs[1], env->regs[13] - 12); in xtensa_underflow12()
112 get_user_ual(env->regs[2], env->regs[13] - 8); in xtensa_underflow12()
114 get_user_ual(env->regs[3], env->regs[13] - 4); in xtensa_underflow12()
/qemu/hw/net/
H A Dtulip.h45 #define CSR5_FBE BIT(13)
95 #define CSR6_ST BIT(13)
121 #define CSR7_SEM BIT(13)
137 #define CSR9_WR BIT(13)
181 #define CSR14_APE BIT(13)
198 #define CSR15_FRL BIT(13)
/qemu/hw/sparc64/
H A Dsun4u_iommu.c36 #define IOMMU_PAGE_SIZE_8K (1ULL << 13)
108 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13; in sun4u_translate_iommu()
111 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13; in sun4u_translate_iommu()
114 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13; in sun4u_translate_iommu()
117 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13; in sun4u_translate_iommu()
120 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13; in sun4u_translate_iommu()
123 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13; in sun4u_translate_iommu()
/qemu/bsd-user/arm/
H A Dtarget_arch_reg.h25 uint32_t r[13];
49 for (i = 0; i < 13; i++) { in target_copy_regs()
52 regs->r_sp = tswapreg(env->regs[13]); in target_copy_regs()
/qemu/tests/tcg/arm/
H A Dfcvt.ref30 13 SINGLE: 6.09755988989491015673e-05 / 0x387fc00d (0 => OK)
31 13 HALF: 0x3ff (0x18 => UNDERFLOW INEXACT )
93 13 SINGLE: 6.09755988989491015673e-05 / 0x387fc00d (0 => OK)
94 13 DOUBLE: 6.09755988989491015673e-05 / 0x003f0ff801a0000000 (0 => OK)
156 13 DOUBLE: 1.17549435082228750797e-38 / 0x003810000000000000 (0 => OK)
157 13 HALF: 0000 (0x10 => INEXACT )
239 13 DOUBLE: 1.17549435082228750797e-38 / 0x003810000000000000 (0 => OK)
240 13 SINGLE: 1.17549435082228750797e-38 / 0x00800000 (0 => OK)
322 13 HALF: 0x7c00 (0 => OK)
323 13 SINGLE: inf / 0x7f800000 (0 => OK)
[all …]
/qemu/tests/tcg/aarch64/
H A Dfcvt.ref30 13 SINGLE: 6.09755988989491015673e-05 / 0x387fc00d (0 => OK)
31 13 HALF: 0x3ff (0x18 => UNDERFLOW INEXACT )
93 13 SINGLE: 6.09755988989491015673e-05 / 0x387fc00d (0 => OK)
94 13 DOUBLE: 6.09755988989491015673e-05 / 0x003f0ff801a0000000 (0 => OK)
156 13 DOUBLE: 1.17549435082228750797e-38 / 0x003810000000000000 (0 => OK)
157 13 HALF: 0000 (0x18 => UNDERFLOW INEXACT )
239 13 DOUBLE: 1.17549435082228750797e-38 / 0x003810000000000000 (0 => OK)
240 13 SINGLE: 1.17549435082228750797e-38 / 0x00800000 (0 => OK)
322 13 HALF: 0x7c00 (0 => OK)
323 13 SINGLE: inf / 0x7f800000 (0 => OK)
[all …]
/qemu/include/hw/i2c/
H A Daspeed_i2c.h100 SHARED_FIELD(BUS_RECOVER_DONE, 13, 1)
126 SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1)
207 /* 13:0 shared with I2CD_CMD[13:0] */
223 FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13)
224 FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13)
226 FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13)
227 FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13)
/qemu/target/arm/tcg/
H A Dt16.decode113 STR_ri 10010 ... ........ @ldst_spec_i rn=13
114 LDR_ri 10011 ... ........ @ldst_spec_i rn=13
124 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP
182 &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4
256 &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
258 &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
/qemu/include/qemu/
H A Dxxhash.h67 v1 = rol32(v1, 13); in qemu_xxhash8()
71 v2 = rol32(v2, 13); in qemu_xxhash8()
75 v3 = rol32(v3, 13); in qemu_xxhash8()
79 v4 = rol32(v4, 13); in qemu_xxhash8()
99 h32 ^= h32 >> 13; in qemu_xxhash8()
/qemu/util/
H A Duuid.c56 uu[8], uu[9], uu[10], uu[11], uu[12], uu[13], uu[14], uu[15]); in qemu_uuid_unparse()
65 uu[13], uu[14], uu[15]); in qemu_uuid_unparse_strdup()
74 if (i == 8 || i == 13 || i == 18 || i == 23) { in qemu_uuid_is_valid()
101 &uu[10], &uu[11], &uu[12], &uu[13], &uu[14], in qemu_uuid_parse()
/qemu/include/hw/char/
H A Dimx_serial.h33 #define URXD_OVRRUN (1<<13) /* 32nd character in RX FIFO */
39 #define USR1_TRDY (1<<13) /* Tx ready */
52 #define USR2_DTRF (1<<13) /* DTR/DSR transition */
67 #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
/qemu/tests/tcg/hexagon/
H A Dtest_round.S4 * but rounded to 13.
18 p0 = cmp.eq(r2, #13); if (p0.new) jump:t test2
/qemu/linux-user/ppc/
H A Dvdso.S104 .cfi_offset 13, 13 * sizeof_reg
140 .cfi_offset 45, offsetof_mcontext_fregs + 13 * sizeof_freg
199 save_vreg 13
/qemu/linux-user/hppa/
H A Dvdso.S69 .cfi_offset 13, offsetof_sigcontext_gr + 13 * 4
108 .cfi_offset 50, offsetof_sigcontext_fr + 13 * 8
109 .cfi_offset 51, offsetof_sigcontext_fr + 13 * 8 + 4
/qemu/linux-user/loongarch64/
H A Dvdso.S70 .cfi_offset 13, B_GR + 13 * 8
104 .cfi_offset 45, B_FR + 13 * 8
/qemu/tests/fp/
H A Dfp-test-log2.c48 printf("test: %016" PRIx64 " %+.13a\n" in compare()
49 " sf: %016" PRIx64 " %+.13a\n" in compare()
50 "libm: %016" PRIx64 " %+.13a\n", in compare()
/qemu/tests/qemu-iotests/
H A D03467 $QEMU_IO -c "write -z 513k 13k" "$TEST_IMG" | _filter_qemu_io
76 $QEMU_IO -c "read -P 0x0 513k 13k" "$TEST_IMG" | _filter_qemu_io
114 $QEMU_IO -c "read -P 0x0 513k 13k" "$TEST_IMG" | _filter_qemu_io
/qemu/target/mips/
H A Dcpu.h181 * Register 12 Register 13 Register 14 Register 15
259 #define CP0_REGISTER_13 13
360 /* CP0 Register 13 */
486 #define CP0TCSt_A 13
585 #define CP0VPEOpt_IWX5 13
625 #define CP0PM_MASK 13
806 * CP0 Register 13
843 #define CP0C0_AT 13 /* 14..13 */
863 #define CP0C1_DS 13 /* 15..13 */
898 #define CP0C3_ULRI 13
[all …]
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c319 FIELD(BNK0_EN_PAD2PAD_LOOPBACK, BNK0_EN_PAD2PAD_LOOPBACK, 0, 13)
361 FIELD(MIO_MST_TRI0, PIN_13_TRI, 13, 1)
388 FIELD(MIO_MST_TRI1, PIN_39_TRI, 13, 1)
421 FIELD(BNK1_EN_PAD2PAD_LOOPBACK, BNK1_EN_PAD2PAD_LOOPBACK, 0, 13)
482 FIELD(SD0_INITPRESET, SD0_INITPRESET, 0, 13)
484 FIELD(SD0_DSPPRESET, SD0_DSPPRESET, 0, 13)
486 FIELD(SD0_HSPDPRESET, SD0_HSPDPRESET, 0, 13)
488 FIELD(SD0_SDR12PRESET, SD0_SDR12PRESET, 0, 13)
490 FIELD(SD0_SDR25PRESET, SD0_SDR25PRESET, 0, 13)
492 FIELD(SD0_SDR50PRSET, SD0_SDR50PRESET, 0, 13)
[all …]
/qemu/include/hw/misc/
H A Dimx6_src.h29 #define SRC_GPR6 13
49 #define CORE0_RST_SHIFT 13

12345678910>>...35