/qemu/target/hexagon/imported/mmvec/ |
H A D | encode_ext.def | 51 DEF_CLASS32(ICLASS_NCJ" 110- 0------- PP------ --------",Z_Load) 52 DEF_CLASS32(ICLASS_NCJ" 110- 1------- PP------ --------",Z_Load_if_Pv) 91 OP(TAGPRE##_nt_qpred, 110,vv,000,sssss) \ 93 OP(TAGPRE##_nt_nqpred,110,vv,001,sssss) \ 97 OP(TAGPRE##_nt_pred, 110,vv,010,ddddd) \ 99 OP(TAGPRE##_nt_npred, 110,vv,011,ddddd) \ 101 OP(TAGPRE##_nt_cur_pred, 110,vv,100,ddddd) \ 103 OP(TAGPRE##_nt_cur_npred, 110,vv,101,ddddd) \ 104 OP(TAGPRE##_tmp_pred, 100,vv,110,ddddd) \ 105 OP(TAGPRE##_nt_tmp_pred, 110,vv,110,ddddd) \ [all …]
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/qemu/target/hexagon/imported/ |
H A D | encode_subinsn.def | 51 DEF_ENC_SUBINSN(SL2_return_tnew, SUBINSN_L2, "111 1101---110") 57 DEF_ENC_SUBINSN(SL2_jumpr31_tnew,SUBINSN_L2, "111 1111---110") 95 DEF_ENC_SUBINSN(SA1_addrx, SUBINSN_A, "110 00ssssxxxx") 96 DEF_ENC_SUBINSN(SA1_cmpeqi, SUBINSN_A, "110 01ssss--ii") 97 DEF_ENC_SUBINSN(SA1_setin1, SUBINSN_A, "110 1--0--dddd") 98 DEF_ENC_SUBINSN(SA1_clrtnew, SUBINSN_A, "110 1--100dddd") 99 DEF_ENC_SUBINSN(SA1_clrfnew, SUBINSN_A, "110 1--101dddd") 100 DEF_ENC_SUBINSN(SA1_clrt, SUBINSN_A, "110 1--110dddd") 101 DEF_ENC_SUBINSN(SA1_clrf, SUBINSN_A, "110 1--111dddd") 145 DEF_PACKED32(P2_PACKED_S2_L1, SUBINSN_S2, SUBINSN_L1, "110B BBBB BBBB BBBB EE0A AAAA AAAA AAAA") [all …]
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H A D | encode_pp.def | 95 STD_PLD_IOENC(rd, "110") /* note dest reg field LSB=0, 1 is reserved */ 109 STD_PST_IOENC(rd, "110","ttttt") 133 STD_LD_GP(rd, "110") /* note dest reg field LSB=0, 1 is reserved */ 142 STD_ST_GP(rd, "110","ttttt") 164 DEF_CLASS32(ICLASS_V4LDST" 110- -------- PP------ --------",StoreImmed) 185 STD_PLD_RRENC(rd, "110") 197 STD_PST_RRENC(rd, "110","ttttt") 232 STD_LD_RRENC(rd, "110") 241 STD_ST_RRENC(rd, "110","ttttt") 254 DEF_ENC32(S4_storei##TAG##_io, ICLASS_V4LDST" 110 -- "OPC" sssss PPIiiiii iIIIIIII") [all …]
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/qemu/target/arm/tcg/ |
H A D | neon-shared.decode | 43 VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \ 46 VCADD 1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \ 49 VSDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 0 .... \ 51 VUDOT 1111 110 00 . 10 .... .... 1101 . q:1 . 1 .... \ 53 VUSDOT 1111 110 01 . 10 .... .... 1101 . q:1 . 0 .... \ 55 VDOT_b16 1111 110 00 . 00 .... .... 1101 . q:1 . 0 .... \ 59 VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \ 61 VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \ 73 VFMA_b16 1111 110 0 0.11 .... .... 1000 . q:1 . 1 .... \
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H A D | m-nocp.decode | 63 VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1 64 VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 65 VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1 66 VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 69 NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
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H A D | mve.decode | 163 VLDSTB_H 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 01 ....... @vldst_wn \ 165 VLDSTB_H 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 01 ....... @vldst_wn \ 167 VLDSTB_W 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 10 ....... @vldst_wn \ 169 VLDSTB_W 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 10 ....... @vldst_wn \ 171 VLDSTH_W 111 . 110 0 a:1 0 1 . 1 ... ... 0 111 10 ....... @vldst_wn \ 173 VLDSTH_W 111 . 110 1 a:1 0 w:1 . 1 ... ... 0 111 10 ....... @vldst_wn \ 412 VIDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 111 . @vidup 413 VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup 418 VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup 419 VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup [all …]
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H A D | sve.decode | 313 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR 345 SQSHL_zpzi 00000100 .. 000 110 100 ... .. ... ..... @rdn_pg_tszimm_shl 373 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn 379 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn 395 FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 396 FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 406 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD 416 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm 431 EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 433 BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 [all …]
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H A D | sme-fa64.decode | 49 FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store 56 # --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers
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H A D | t16.decode | 81 LDRB_rr 0101 110 ... ... ... @ldst_rr 154 ADD_rri 0001 110 ... ... ... @addsub_2i 257 LDM_t16 1011 110 ......... \
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H A D | vfp.decode | 25 # 1110 110. .... .... .... 101. .... .... 242 VCVT_hp_int ---- 1110 1.11 110 s:1 .... 1001 rz:1 1.0 .... \ 244 VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ 246 VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
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/qemu/target/riscv/ |
H A D | insn32.decode | 139 bltu ....... ..... ..... 110 ..... 1100011 @b 154 ori ............ ..... 110 ..... 0010011 @i 167 or 0000000 ..... ..... 110 ..... 0110011 @r 180 csrrsi ............ ..... 110 ..... 1110011 @csr 184 lwu ............ ..... 110 ..... 0000011 @i 231 rem 0000001 ..... ..... 110 ..... 0110011 @r 238 remw 0000001 ..... ..... 110 ..... 0111011 @r 245 remd 0000001 ..... ..... 110 ..... 1111011 @r 369 vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 373 vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm [all …]
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H A D | xthead.decode | 104 th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx 105 th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx 106 th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx 107 th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx
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H A D | XVentanaCondOps.decode | 24 vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r
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H A D | insn16.decode | 127 sw 110 ... ... .. ... 00 @cs_w 160 beq 110 ... ... ..... 01 @cb_z 208 sw 110 . ..... ..... 10 @c_swsp
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/qemu/tests/qemu-iotests/ |
H A D | 204.out | 9 110 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) 31 16/1000 bytes allocated at offset 110 MiB 33 110 MiB (0x6e00000) bytes allocated at offset 0 bytes (0x0) 34 18 MiB (0x1200000) bytes not allocated at offset 110 MiB (0x6e00000)
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H A D | 204 | 57 $QEMU_IO -c "write -P 22 0 110M" "$TEST_IMG" | _filter_qemu_io 108 echo read -P 11 110M 18M
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H A D | 110.out | 1 QA output created by 110
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H A D | 046 | 146 write -c -P 110 0xb0000 0x10000 249 echo read -P 110 0xb8000 0x8000
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/qemu/target/mips/tcg/ |
H A D | msa.decode | 56 BZ 010001 110 .. ..... ................ @bz 81 LDI 011110 110 .. .......... ..... 000111 @ldi 89 BINSLI 011110 110 ....... ..... ..... 001001 @bit 103 BINSL 011110 110.. ..... ..... ..... 001101 @3r 112 MAX_A 011110 110.. ..... ..... ..... 001110 @3r 127 AVER_S 011110 110.. ..... ..... ..... 010000 @3r 142 MOD_S 011110 110.. ..... ..... ..... 010010 @3r 158 ILVEV 011110 110 .. ..... ..... ..... 010100 @3r 166 HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
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/qemu/target/hppa/ |
H A D | insns.decode | 454 bv 111010 b:5 x:5 110 00000000000 n:1 0 455 bve 111010 b:5 00000 110 10000000000 n:1 - l=0 493 @f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 495 @f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 505 fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 512 fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 519 fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 526 fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 583 fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 584 fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 [all …]
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/qemu/hw/timer/ |
H A D | imx_gpt.c | 81 CLK_32k, /* 110 ipg_clk_32k */ 92 CLK_NONE, /* 110 not defined */ 103 CLK_NONE, /* 110 not defined */ 114 CLK_NONE, /* 110 not defined */ 125 CLK_NONE, /* 110 not defined */ 136 CLK_NONE, /* 110 not defined */
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/qemu/tests/unit/ |
H A D | test-interval-tree.c | 113 * but only one node with exactly [110,190]. in test_find_one_range_many() 115 nodes[0].start = 110; in test_find_one_range_many() 133 g_assert(interval_tree_iter_first(&root, 100, 110) == &nodes[0]); in test_find_one_range_many()
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/qemu/target/avr/ |
H A D | insn.decode | 93 JMP 1001 010 ..... 110 . imm=%imm_call 104 SBRC 1111 110 rr:5 0 bit:3
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/qemu/tests/tcg/aarch64/ |
H A D | sme-smopa-1.c | 7 { 110, 134, 158, 182 }, in main()
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/qemu/linux-user/loongarch64/ |
H A D | syscall.tbl | 140 110 time32 timer_settime sys_timer_settime32 141 110 64 timer_settime sys_timer_settime
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