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/qemu/target/arm/tcg/
H A Dt32.decode129 UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
150 CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi
151 ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi
196 CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot
197 ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot
275 SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm
304 SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm
332 QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm
333 QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm
334 QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm
[all …]
H A Dneon-shared.decode43 VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \
46 VCADD 1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \
59 VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
61 VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
73 VFMA_b16 1111 110 0 0.11 .... .... 1000 . q:1 . 1 .... \
76 VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
78 VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
94 VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \
96 VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \
98 VFMA_b16_scal 1111 1110 0.11 .... .... 1000 . q:1 . 1 . vm:3 \
/qemu/contrib/plugins/
H A Dips.c25 #define NSEC_IN_ONE_SEC (1000 * 1000 * 1000)
29 static uint64_t max_insn_per_second = 1000 * 1000 * 1000; /* ips per core, per second */
46 return g_get_real_time() * 1000; in now_ns()
70 int64_t sleep_us = time_advance_ns / 1000; in update_system_time()
139 { "k", 1000 },
140 { "m", 1000 * 1000 },
141 { "g", 1000 * 1000 * 1000 },
/qemu/tests/data/hex-loader/
H A Dtest.hex12 :1000a000a0a1a2a3a4a5a6a7a8a9aaabacadaeafd8
13 :1000b000b0b1b2b3b4b5b6b7b8b9babbbcbdbebfc8
14 :1000c000c0c1c2c3c4c5c6c7c8c9cacbcccdcecfb8
15 :1000d000d0d1d2d3d4d5d6d7d8d9dadbdcdddedfa8
16 :1000e000e0e1e2e3e4e5e6e7e8e9eaebecedeeef98
17 :1000f000f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff88
/qemu/tests/unit/
H A Dtest-xbzrle.c50 buffer[1000 + i] = i; in test_encode_decode_zero()
53 buffer[1000 + diff_len + 3] = 103; in test_encode_decode_zero()
54 buffer[1000 + diff_len + 5] = 105; in test_encode_decode_zero()
74 test[1000 + i] = i + 4; in test_encode_decode_unchanged()
77 test[1000 + diff_len + 3] = 107; in test_encode_decode_unchanged()
78 test[1000 + diff_len + 5] = 109; in test_encode_decode_unchanged()
144 buffer[1000 + i] = i; in encode_decode_range()
145 test[1000 + i] = i + 4; in encode_decode_range()
148 buffer[1000 + diff_len + 3] = 103; in encode_decode_range()
149 test[1000 + diff_len + 3] = 107; in encode_decode_range()
[all …]
H A Drcutorture.c75 #define RCU_READ_RUN 1000
127 g_usleep(1000); in rcu_read_perf_test()
153 g_usleep(1000); in rcu_update_perf_test()
175 g_usleep(1000); in perftestrun()
184 ((duration * 1000*1000*1000.*(double)nreaders) / in perftestrun()
186 ((duration * 1000*1000*1000.*(double)nupdaters) / in perftestrun()
257 g_usleep(1000); in rcu_read_stress_test()
309 g_usleep(1000); in rcu_update_stress_test()
351 g_usleep(1000); in rcu_fake_update_stress_test()
355 g_usleep(1000); in rcu_fake_update_stress_test()
/qemu/target/avr/
H A Dinsn.decode98 RET 1001 0101 0000 1000
99 RETI 1001 0101 0001 1000
147 LPM1 1001 0101 1100 1000
150 ELPM1 1001 0101 1101 1000
153 SPM 1001 0101 1110 1000
154 SPMX 1001 0101 1111 1000
172 CBI 1001 1000 reg:5 bit:3
175 BSET 1001 0100 0 bit:3 1000
176 BCLR 1001 0100 1 bit:3 1000
181 BREAK 1001 0101 1001 1000
[all …]
/qemu/tests/qemu-iotests/
H A D151265 self.vm.qtest(f'clock_step {1 * 1000 * 1000 * 1000}')
274 self.vm.qtest(f'clock_step {1 * 1000 * 1000 * 1000}')
302 self.vm.qtest(f'clock_step {1 * 1000 * 1000 * 1000}')
338 step = math.ceil(1 * 1000 * 1000 * 1000 / self.iops)
357 step = math.ceil(1 * 1000 * 1000 * 1000 / self.iops)
399 self.vm.qtest(f'clock_step {1 * 1000 * 1000 * 1000}')
H A D204.out12 wrote 131072/131072 bytes at offset 1000
14 read 131072/131072 bytes at offset 1000
31 16/1000 bytes allocated at offset 110 MiB
37 read 1000/1000 bytes at offset 0
38 1000 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
39 read 131072/131072 bytes at offset 1000
H A D177.out12 wrote 131072/131072 bytes at offset 1000
14 read 131072/131072 bytes at offset 1000
30 read 1000/1000 bytes at offset 0
31 1000 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
32 read 131072/131072 bytes at offset 1000
H A D241.out10 [{ "start": 0, "length": 1000, "depth": 0, "present": true, "zero": false, "data": true, "compresse…
11 { "start": 1000, "length": 24, "depth": 0, "present": true, "zero": true, "data": false, "compresse…
34 [{ "start": 0, "length": 1000, "depth": 0, "present": true, "zero": false, "data": true, "compresse…
35 { "start": 1000, "length": 24, "depth": 0, "present": true, "zero": true, "data": false, "compresse…
H A D20464 -c "write -P 33 1000 128k" -c "read -P 33 1000 128k" | _filter_qemu_io
91 -c "alloc 1 1" -c "alloc 0x6dffff0 1000" -c "alloc 127m 5P" \
99 echo read -P 22 0 1000
100 echo read -P 33 1000 128k
H A D17763 -c "write -P 33 1000 128k" -c "read -P 33 1000 128k" | _filter_qemu_io
101 echo read -P 22 0 1000
102 echo read -P 33 1000 128k
/qemu/hw/avr/
H A Darduino.c84 amc->xtal_hz = 16 * 1000 * 1000; in arduino_duemilanove_class_init()
99 amc->xtal_hz = 16 * 1000 * 1000; in arduino_uno_class_init()
114 amc->xtal_hz = 16 * 1000 * 1000; in arduino_mega_class_init()
129 amc->xtal_hz = 16 * 1000 * 1000; /* CSTCE16M0V53-R0 */ in arduino_mega2560_class_init()
/qemu/include/hw/net/
H A Dmii.h34 #define MII_CTRL1000 9 /* 1000BASE-T control */
35 #define MII_STAT1000 10 /* 1000BASE-T status */
56 #define MII_BMCR_SPEED1000 (1 << 6) /* MSB of Speed (1000) */
101 #define MII_CTRL1000_FULL (1 << 9) /* 1000BASE-T full duplex */
102 #define MII_CTRL1000_HALF (1 << 8) /* 1000BASE-T half duplex */
106 #define MII_STAT1000_FULL (1 << 11) /* 1000BASE-T full duplex */
107 #define MII_STAT1000_HALF (1 << 10) /* 1000BASE-T half duplex */
109 #define MII_EXTSTAT_1000T_FD (1 << 13) /* 1000BASE-T Full Duplex */
110 #define MII_EXTSTAT_1000T_HD (1 << 12) /* 1000BASE-T Half Duplex */
/qemu/tests/qtest/
H A Dcmsdk-apb-dualtimer-test.c53 writel(TIMER_BASE + TIMER1LOAD, 1000); in test_dualtimer()
62 /* Just past the 1000th tick: timer should have fired */ in test_dualtimer()
86 /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ in test_prescale()
87 writel(TIMER_BASE + TIMER2LOAD, 1000); in test_prescale()
97 /* Just past the 1000th tick: timer should have fired */ in test_prescale()
104 g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000); in test_prescale()
H A Dtest-netfilter.c26 " 'interval': 1000" in add_one_netfilter()
53 " 'interval': 1000" in remove_netdev_with_one_netfilter()
90 " 'interval': 1000" in add_multi_netfilter()
103 " 'interval': 1000" in add_multi_netfilter()
138 " 'interval': 1000" in remove_netdev_with_multi_netfilter()
151 " 'interval': 1000" in remove_netdev_with_multi_netfilter()
H A Dcmsdk-apb-watchdog-test.c92 writel(wdog_base + WDOGLOAD, 1000); in test_watchdog()
99 /* Just past the 1000th tick: timer should have fired */ in test_watchdog()
106 g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1000); in test_watchdog()
113 g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1000); in test_watchdog()
138 writel(WDOG_BASE + WDOGLOAD, 1000); in test_clock_change()
151 /* Just past the 1000th tick: timer should have fired */ in test_clock_change()
159 g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); in test_clock_change()
166 g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); in test_clock_change()
200 clock_step(1000 * tick + 1); in test_watchdog_reset()
211 clock_step(1000 * tick + 1); in test_watchdog_reset()
[all …]
H A Dcmsdk-apb-timer-test.c32 /* Start timer: will fire after 40 * 1000 == 40000 ns */ in test_timer()
33 writel(TIMER_BASE + RELOAD, 1000); in test_timer()
41 /* Just past the 1000th tick: timer should have fired */ in test_timer()
48 g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000); in test_timer()
H A Dadm1272-test.c101 c.b = c.b * 1000; in adm1272_millivolts_to_direct()
109 c.b = c.b * 1000; in adm1272_direct_to_millivolts()
118 c.m = c.m * ADM1272_SHUNT / 1000; /* micro-ohms */ in adm1272_milliamps_to_direct()
119 c.b = c.b * 1000; in adm1272_milliamps_to_direct()
127 c.m = c.m * ADM1272_SHUNT / 1000; in adm1272_direct_to_milliamps()
128 c.b = c.b * 1000; in adm1272_direct_to_milliamps()
136 c.m = c.m * ADM1272_SHUNT / 1000; in adm1272_watts_to_direct()
143 c.m = c.m * ADM1272_SHUNT / 1000; in adm1272_direct_to_watts()
256 adm1272_direct_to_millivolts(adm1272_millivolts_to_direct(1000)); in test_tx_rx()
257 qmp_adm1272_set(TEST_ID, "vin", 1000); in test_tx_rx()
/qemu/target/hexagon/imported/
H A Dencode_pp.def38 #define ICLASS_S2op "1000"
371 DEF_ANTICLASS32(ICLASS_LD" 1000 000----- PP------ --------",LD_ADDR_POST_CIRC_IMMED)
745 DEF_FIELDROW_DESC32( ICLASS_CR" 1000 -------- PP------ --------","[#8] Rdd=Css ")
746 DEF_ENC32(A4_tfrcpp, ICLASS_CR" 1000 000sssss PP------ ---ddddd")
765 DEF_ENC32(C2_any8, ICLASS_CR" 1011 1000--ss PP0----- ------dd")
904 DEF_FIELDROW_DESC32(ICLASS_M" 1000 -------- PP------ --------","[#8] Rdd=(Rss,Rtt)")
905 MPY_ENC(M2_vrcmpyi_s0, "1000","ddddd","0","0","0","0","00")
906 MPY_ENC(M2_vdmpys_s0, "1000","ddddd","1","0","0","0","00")
907 MPY_ENC(M2_vdmpys_s1, "1000","ddddd","1","0","0","1","00")
908 MPY_ENC(M2_vrcmpyi_s0c, "1000","ddddd","0","0","1","0","00")
[all …]
/qemu/python/qemu/utils/
H A Dqom_fuse.py166 'st_uid': 1000,
167 'st_gid': 1000,
179 'st_uid': 1000,
180 'st_gid': 1000,
192 'st_uid': 1000,
193 'st_gid': 1000,
/qemu/crypto/
H A Dpbkdf.c69 *val_ms = ((info.user_time.seconds * 1000ll) + in qcrypto_pbkdf2_get_thread_cpu()
70 (info.user_time.microseconds / 1000)); in qcrypto_pbkdf2_get_thread_cpu()
79 *val_ms = ((ru.ru_utime.tv_sec * 1000ll) + in qcrypto_pbkdf2_get_thread_cpu()
80 (ru.ru_utime.tv_usec / 1000)); in qcrypto_pbkdf2_get_thread_cpu()
152 iterations = (iterations * 1000 / delta_ms); in threaded_qcrypto_pbkdf2_count_iters()
157 iterations = iterations * 1000 / delta_ms; in threaded_qcrypto_pbkdf2_count_iters()
/qemu/target/rx/
H A Dinsns.decode170 BRA 0011 1000 .... .... .... .... @b3_bra_w
223 DIV_ir 1111 1101 0111 ..00 1000 .... @b3_rd_li
228 DIV_mr 0000 0110 ..10 00.. 0000 1000 .... .... @b4_rd_ldmi
258 FADD_mr 1111 1100 1000 10.. .... .... @b3_rd_ld_ul
264 FCMP_mr 1111 1100 1000 01.. .... .... @b3_rd_ld_ul
276 FMUL_mr 1111 1100 1000 11.. .... .... @b3_rd_ld_ul
282 FSUB_mr 1111 1100 1000 00.. .... .... @b3_rd_ld_ul
324 MOV_rm 1000 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=0
330 MOV_mr 1000 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=0
348 MOV_im 1111 1000 rd:4 .. sz:2 dsp=0 imm=%b2_li_2
[all …]
/qemu/tests/qemu-iotests/tests/
H A Dmirror-change-copy-mode144 self.vm.qtest(f'clock_step {1 * 1000 * 1000 * 1000}')
161 self.vm.qtest(f'clock_step {100 * 1000 * 1000}')

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