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/qemu/target/hexagon/imported/mmvec/
H A Dencode_ext.def90 OP(TAGPRE##_qpred, 100,vv,000,sssss) \
92 OP(TAGPRE##_nqpred, 100,vv,001,sssss) \
96 OP(TAGPRE##_pred, 100,vv,010,ddddd) \
98 OP(TAGPRE##_npred, 100,vv,011,ddddd) \
100 OP(TAGPRE##_cur_pred, 100,vv,100,ddddd) \
101 OP(TAGPRE##_nt_cur_pred, 110,vv,100,ddddd) \
102 OP(TAGPRE##_cur_npred, 100,vv,101,ddddd) \
104 OP(TAGPRE##_tmp_pred, 100,vv,110,ddddd) \
106 OP(TAGPRE##_tmp_npred, 100,vv,111,ddddd) \
205 DEF_ENC(V6_vaddcarrysat, ICLASS_CJ" 1 101 100 vvvvv PP 1 uuuuu 0ss ddddd") //
[all …]
/qemu/target/riscv/
H A Dxthead.decode126 th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc
127 th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc
128 th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc
129 th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc
130 th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc
131 th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc
132 th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc
133 th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc
134 th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc
135 th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc
[all …]
H A Dinsn16.decode152 srli 100 . 00 ... ..... 01 @c_shift
153 srai 100 . 01 ... ..... 01 @c_shift
154 andi 100 . 10 ... ..... 01 @c_andi
155 sub 100 0 11 ... 00 ... 01 @cs_2
156 xor 100 0 11 ... 01 ... 01 @cs_2
157 or 100 0 11 ... 10 ... 01 @cs_2
158 and 100 0 11 ... 11 ... 01 @cs_2
169 subw 100 1 11 ... 00 ... 01 @cs_2
170 addw 100 1 11 ... 01 ... 01 @cs_2
183 illegal 100 0 00000 00000 10 # c.jr, RES rs1=0
[all …]
H A Dinsn32.decode137 blt ....... ..... ..... 100 ..... 1100011 @b
144 lbu ............ ..... 100 ..... 0000011 @i
152 xori ............ ..... 100 ..... 0010011 @i
164 xor 0000000 ..... ..... 100 ..... 0110011 @r
213 sq ............ ..... 100 ..... 0100011 @s
229 div 0000001 ..... ..... 100 ..... 0110011 @r
236 divw 0000001 ..... ..... 100 ..... 0111011 @r
243 divd 0000001 ..... ..... 100 ..... 1111011 @r
347 hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
348 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
[all …]
/qemu/target/arm/tcg/
H A Dsve.decode303 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
311 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
341 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
342 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
343 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
344 ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
345 SQSHL_zpzi 00000100 .. 000 110 100 ... .. ... ..... @rdn_pg_tszimm_shl
346 UQSHL_zpzi 00000100 .. 000 111 100 ... .. ... ..... @rdn_pg_tszimm_shl
347 SRSHR 00000100 .. 001 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
348 URSHR 00000100 .. 001 101 100 ... .. ... ..... @rdn_pg_tszimm_shr
[all …]
/qemu/tests/qemu-iotests/
H A D086.out11 (0.00/100%)
12 (25.00/100%)
13 (50.00/100%)
14 (75.00/100%)
15 (100.00/100%)
16 (100.00/100%)
H A D061.out500 (0.00/100%)
501 (12.50/100%)
502 (25.00/100%)
503 (37.50/100%)
504 (50.00/100%)
505 (62.50/100%)
506 (75.00/100%)
507 (87.50/100%)
508 (100.00/100%)
509 (100.00/100%)
[all …]
H A D07769 sleep 100
88 sleep 100
103 sleep 100
117 sleep 100
131 sleep 100
145 sleep 100
156 sleep 100
171 sleep 100
182 sleep 100
H A D149.out10 qemu-io -c write -P 0xa7 100M 10M --image-opts driver=host_device,filename=/dev/mapper/qiotest-145-…
23 qemu-io -c read -P 0xa7 100M 10M --object secret,id=sec0,data=MTIzNDU2,format=base64 --image-opts d…
33 qemu-io -c write -P 0x91 100M 10M --object secret,id=sec0,data=MTIzNDU2,format=base64 --image-opts …
46 qemu-io -c read -P 0x91 100M 10M --image-opts driver=host_device,filename=/dev/mapper/qiotest-145-a…
68 qemu-io -c write -P 0xa7 100M 10M --image-opts driver=host_device,filename=/dev/mapper/qiotest-145-…
81 qemu-io -c read -P 0xa7 100M 10M --object secret,id=sec0,data=MTIzNDU2,format=base64 --image-opts d…
91 qemu-io -c write -P 0x91 100M 10M --object secret,id=sec0,data=MTIzNDU2,format=base64 --image-opts …
104 qemu-io -c read -P 0x91 100M 10M --image-opts driver=host_device,filename=/dev/mapper/qiotest-145-a…
128 qemu-io -c write -P 0xa7 100M 10M --image-opts driver=host_device,filename=/dev/mapper/qiotest-145-…
141 qemu-io -c read -P 0xa7 100M 10M --object secret,id=sec0,data=MTIzNDU2,format=base64 --image-opts d…
[all …]
/qemu/target/hexagon/imported/
H A Dencode_subinsn.def49 DEF_ENC_SUBINSN(SL2_return_t, SUBINSN_L2, "111 1101---100")
55 DEF_ENC_SUBINSN(SL2_jumpr31_t, SUBINSN_L2, "111 1111---100")
68 DEF_ENC_SUBINSN(SS2_storewi0, SUBINSN_S2, "100 00ssssiiii")
69 DEF_ENC_SUBINSN(SS2_storewi1, SUBINSN_S2, "100 01ssssiiii")
70 DEF_ENC_SUBINSN(SS2_storebi0, SUBINSN_S2, "100 10ssssiiii")
71 DEF_ENC_SUBINSN(SS2_storebi1, SUBINSN_S2, "100 11ssssiiii")
84 DEF_ENC_SUBINSN(SA1_tfr, SUBINSN_A, "100 00ssssdddd")
85 DEF_ENC_SUBINSN(SA1_inc, SUBINSN_A, "100 01ssssdddd")
86 DEF_ENC_SUBINSN(SA1_and1, SUBINSN_A, "100 10ssssdddd")
87 DEF_ENC_SUBINSN(SA1_dec, SUBINSN_A, "100 11ssssdddd")
[all …]
H A Dencode_pp.def94 STD_PLD_IOENC(ri, "100")
108 STD_PST_IOENC(ri, "100","ttttt")
132 STD_LD_GP(ri, "100")
141 STD_ST_GP(ri, "100","ttttt")
162 DEF_CLASS32(ICLASS_V4LDST" 100- -------- PP------ --------",Pred_StoreImmed)
184 STD_PLD_RRENC(ri, "100")
196 STD_PST_RRENC(ri, "100","ttttt")
209 DEF_ENC32(S4_storei##TAG##t_io, ICLASS_V4LDST" 100 00 "OPC" sssss PPIiiiii ivvIIIII")\
210 DEF_ENC32(S4_storei##TAG##f_io, ICLASS_V4LDST" 100 01 "OPC" sssss PPIiiiii ivvIIIII")\
211 DEF_ENC32(S4_storei##TAG##tnew_io, ICLASS_V4LDST" 100 10 "OPC" sssss PPIiiiii ivvIIIII")\
[all …]
/qemu/tests/qtest/
H A Dtest-arm-mptimer.c184 timer_load(100); in test_timer_periodic()
190 g_assert_cmpuint(timer_counter(), ==, 100 - repeat); in test_timer_periodic()
506 TIMER_BLOCK_STEP(scaler, 100); in test_timer_nonzero_load_oneshot_to_zero()
527 TIMER_BLOCK_STEP(scaler, 100); in test_timer_nonzero_load_periodic_to_zero()
541 TIMER_BLOCK_STEP(scaler, 100); in test_timer_set_periodic_counter_on_the_fly()
543 g_assert_cmpuint(timer_counter(), ==, UINT32_MAX / 2 - 100); in test_timer_set_periodic_counter_on_the_fly()
548 TIMER_BLOCK_STEP(scaler, 100); in test_timer_set_periodic_counter_on_the_fly()
550 g_assert_cmpuint(timer_counter(), ==, UINT32_MAX - 100); in test_timer_set_periodic_counter_on_the_fly()
567 TIMER_BLOCK_STEP(scaler, 100); in test_timer_enable_and_set_counter()
569 g_assert_cmpuint(timer_counter(), ==, UINT32_MAX - 100); in test_timer_enable_and_set_counter()
[all …]
H A Dsse-timer-test.c85 clock_step_ticks(100); in test_counter()
90 clock_step_ticks(100); in test_counter()
91 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 100); in test_counter()
126 clock_step_ticks(100); in test_timer()
127 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 100); in test_timer()
155 clock_step_ticks(100); in test_timer()
157 clock_step_ticks(100); in test_timer()
162 clock_step_ticks(100); in test_timer()
168 clock_step_ticks(100); in test_timer()
H A Dvirtio-net-test.c202 " 'initial': 20, 'max': 100," in announce_self()
221 " 'initial': 20, 'max': 100," in announce_self()
230 /* 30 packets, max gap 100ms, * 4 for wiggle */ in announce_self()
231 deadline = start + 1000 * (100 * 30 * 4); in announce_self()
253 if ((now - last_rxt) > (1000 * 100 * 4)) { in announce_self()
258 /* 100ms */ in announce_self()
259 g_usleep(1000 * 100); in announce_self()
/qemu/tests/unit/
H A Dtest-thread-pool.c117 WorkerTestData data[100]; in test_submit_many()
121 for (i = 0; i < 100; i++) { in test_submit_many()
127 active = 100; in test_submit_many()
131 for (i = 0; i < 100; i++) { in test_submit_many()
139 WorkerTestData data[100]; in do_test_cancel()
149 for (i = 0; i < 100; i++) { in do_test_cancel()
159 active = 100; in do_test_cancel()
166 g_assert_cmpint(active, ==, 100); in do_test_cancel()
172 for (i = 0; i < 100; i++) { in do_test_cancel()
184 g_assert_cmpint(num_canceled, <, 100); in do_test_cancel()
[all …]
H A Dtest-interval-tree.c130 g_assert(interval_tree_iter_first(&root, 100, 199) == &nodes[0]); in test_find_one_range_many()
131 g_assert(interval_tree_iter_next(&nodes[0], 100, 199) == NULL); in test_find_one_range_many()
132 g_assert(interval_tree_iter_first(&root, 100, 109) == NULL); in test_find_one_range_many()
133 g_assert(interval_tree_iter_first(&root, 100, 110) == &nodes[0]); in test_find_one_range_many()
143 g_assert(interval_tree_iter_first(&root, 100, 300) == &nodes[0]); in test_find_one_range_many()
147 g_assert(interval_tree_iter_first(&root, 100, 199) == NULL); in test_find_one_range_many()
H A Dtest-timed-average.c50 for (i = 0; i < 100; i++) { in test_average()
61 my_clock_value += NANOSECONDS_PER_SECOND * 100; in test_average()
70 for (i = 0; i < 100; i++) { in test_average()
/qemu/util/
H A Dqemu-progress.c46 printf(" (%3.2f/100%%)\r", state.current); in progress_simple_print()
71 fprintf(stderr, " (%3.2f/100%%)\n", state.current); in progress_dummy_print()
136 * of @max. I.e. the delta is @delta * @max / 100. This allows
149 current = state.current + delta / 100 * max; in qemu_progress_print()
151 if (current > 100) { in qemu_progress_print()
152 current = 100; in qemu_progress_print()
158 current == 100 || current == 0) { in qemu_progress_print()
/qemu/tests/qtest/migration/
H A Dbootfile.h16 #define X86_TEST_MEM_END (100 * 1024 * 1024)
20 #define S390_TEST_MEM_END (100 * 1024 * 1024)
24 #define PPC_TEST_MEM_END (100 * 1024 * 1024)
29 #define ARM_TEST_MEM_END (0x40000000 + 100 * 1024 * 1024)
/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmilatency.py255 "10us < t <= 100us",
56 "100us < t <= 1ms",
58 "10ms < t <= 100ms",
59 "100ms < t <= 1s ",
61 "10s < t <= 100s ",
62 "100s < t ",
/qemu/docs/
H A Dthrottle.txt51 of 100 IOPS with the following -drive line:
53 -drive file=hd0.qcow2,throttling.iops-total=100
61 "iops": 100,
87 we want to configure a drive with a basic limit of 100 IOPS and allow
92 throttling.iops-total=100,
101 "iops": 100,
113 IOPS for 1 minute before it's throttled down to 100 IOPS.
231 iops-total=100
235 - Water leaks from the bucket at a rate of 100 IOPS.
241 unset as well. In this case the bucket size is 100.
[all …]
/qemu/include/hw/net/
H A Dmii.h48 #define MII_BMCR_SPEED100 (1 << 13) /* LSB of Speed (100) */
58 #define MII_BMSR_100T4 (1 << 15) /* Can do 100mbps T4 */
59 #define MII_BMSR_100TX_FD (1 << 14) /* Can do 100mbps, full-duplex */
60 #define MII_BMSR_100TX_HD (1 << 13) /* Can do 100mbps, half-duplex */
63 #define MII_BMSR_100T2_FD (1 << 10) /* Can do 100mbps T2, full-duplex */
64 #define MII_BMSR_100T2_HD (1 << 9) /* Can do 100mbps T2, half-duplex */
/qemu/docs/specs/
H A Dedu.rst116 Example of transferring a 100 byte block to and from the buffer using a given
123 100 -> DMA transfer count
131 addr+100 -> DMA destination address
132 100 -> DMA transfer count
/qemu/include/block/
H A Daccounting.h61 * 10 50 100
65 * .boundaries = {10, 50, 100},
74 * [0, 10), [10, 50), [50, 100), [100, +inf)
/qemu/docs/sphinx-static/
H A Dtheme_overrides.css12 font-size: 100%;
54 font-size: 100%;
66 font-size: 100%;
158 .rst-content table.docutils caption { text-align: left; font-size: 100%; }
162 * - captions should have 100% (not 85%) font size
172 font-size: 100%;

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