Searched +full:1 +full:- +full:mdio (Results 1 – 12 of 12) sorted by relevance
7 * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite36 #include "hw/qdev-properties.h"37 #include "hw/qdev-properties-system.h"51 TX_GIE = 1,82 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite"100 UnimplementedDeviceState mdio; member107 if (s->port[0].reg.tx_gie & GIE_GIE) { in eth_pulse_irq()108 qemu_irq_pulse(s->irq); in eth_pulse_irq()114 return extract64(addr, 11, 1); in addr_to_port_index()119 return memory_region_get_ram_ptr(&s->port[port_index].txbuf); in txbuf_ptr()[all …]
4 Copyright(c) 1999 - 2006 Intel Corporation.23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497115 * RW - register is both readable and writable116 * RO - register is read only117 * WO - register is write only118 * R/clr - register is read only and is cleared when read119 * A - register array121 #define E1000_CTRL 0x00000 /* Device Control - RW */122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */[all …]
2 * QEMU model of Xilinx AXI-Ethernet.35 #include "hw/qdev-properties.h"41 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"42 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"43 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"55 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */56 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */57 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */80 case 1: in tdk_read()81 if (!phy->link) { in tdk_read()[all …]
4 * Copyright (C) 2016-2017, IBM Corporation.11 * COPYING file in the top-level directory.24 #include "hw/qdev-properties.h"61 * values below are offset by - FTGMAC100_REG_HIGH_OFFSET from datasheet64 #define FTGMAC100_NPTXR_BADR_HIGH (0x17C - FTGMAC100_REG_HIGH_OFFSET)65 #define FTGMAC100_HPTXR_BADR_HIGH (0x184 - FTGMAC100_REG_HIGH_OFFSET)66 #define FTGMAC100_RXR_BADR_HIGH (0x18C - FTGMAC100_REG_HIGH_OFFSET)71 #define FTGMAC100_INT_RPKT_BUF (1 << 0)72 #define FTGMAC100_INT_RPKT_FIFO (1 << 1)73 #define FTGMAC100_INT_NO_RXBUF (1 << 2)[all …]
7 * Copyright 2017 Mark Cave-Ayland12 #include "hw/qdev-properties.h"150 #define MAC_ADDR1 0x0084UL /* MAC Address 1 Register */170 #define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */171 #define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */243 mask = s->gregs[GREG_IMASK >> 2]; in sungem_eval_irq()244 stat = s->gregs[GREG_STAT >> 2] & ~GREG_STAT_TXNR; in sungem_eval_irq()246 pci_set_irq(PCI_DEVICE(s), 1); in sungem_eval_irq()256 stat = s->gregs[GREG_STAT >> 2]; in sungem_update_status()262 s->gregs[GREG_STAT >> 2] = stat; in sungem_update_status()[all …]
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>11 /dts-v1/;14 #address-cells = <2>;15 #size-cells = <1>;18 dcr-parent = <&{/cpus/cpu@0}>;28 #address-cells = <1>;29 #size-cells = <0>;35 clock-frequency = <0>; /* Filled in by U-Boot */36 timebase-frequency = <0>; /* Filled in by U-Boot */37 i-cache-line-size = <32>;[all …]
5 * SPDX-License-Identifier: GPL-2.0+8 /dts-v1/;11 #address-cells = < 0x01 >;12 #size-cells = < 0x01 >;22 ethernet0 = "/axi/axi-ethernet@82780000";28 stdout-path = "/axi/serial@83e00000";32 #address-cells = < 0x01 >;34 #size-cells = < 0x00 >;37 clock-frequency = < 0xbebc200 >;38 compatible = "xlnx,microblaze-8.10.a";[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */19 #include "standard-headers/linux/const.h"20 #include "standard-headers/linux/types.h"21 #include "standard-headers/linux/if_ether.h"26 * have the same layout for 32-bit and 64-bit userland.38 * struct ethtool_cmd - DEPRECATED, link control and status43 * interface supports autonegotiation or auto-detection.44 * Read-only.48 * auto-detection.49 * @speed: Low bits of the speed, 1Mb units, 0 to INT_MAX or SPEED_UNKNOWN[all …]
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2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>6 * Based on hw/arm/fsl-imx7.c21 #include "hw/arm/fsl-imx6ul.h"23 #include "hw/usb/imx-usb-phy.h"26 #include "qemu/error-report.h"28 #include "target/arm/cpu-qom.h"38 object_initialize_child(obj, "cpu0", &s->cpu, in fsl_imx6ul_init()39 ARM_CPU_TYPE_NAME("cortex-a7")); in fsl_imx6ul_init()44 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, in fsl_imx6ul_init()50 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM); in fsl_imx6ul_init()[all …]
8 * Based on hw/arm/fsl-imx6.c23 #include "hw/arm/fsl-imx7.h"27 #include "qemu/error-report.h"29 #include "target/arm/cpu-qom.h"43 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { in fsl_imx7_init()45 object_initialize_child(obj, name, &s->cpu[i], in fsl_imx7_init()46 ARM_CPU_TYPE_NAME("cortex-a7")); in fsl_imx7_init()52 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, in fsl_imx7_init()60 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); in fsl_imx7_init()68 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT); in fsl_imx7_init()[all …]
1 00-INDEX: 33312 1d: 409613 1.Intro: 1496855 3.Early-stage: 999356 3w-9xxx.c: 7731857 3w-9xxx.h: 2635758 3w-xxxx.c: 8522759 3w-xxxx.h: 1684671 4level-fixup.h: 1028110 6xx-suspend.S: 1086[all …]