1\-l2 (full) in projects: linux-6.8 - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:1 +full:- +full:l2 (Results 1 – 25 of 1061) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...43

/linux-6.8/drivers/isdn/mISDN/
D	layer2.c	1 // SPDX-License-Identifier: GPL-2.0-only 59 #define L2_EVENT_COUNT (EV_L2_FRAME_ERROR + 1) 92 struct layer2 l2 = fi->userdata; in l2m_debug() local 104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug() 105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug() 111 l2headersize(struct layer2 l2, int ui) in l2headersize() argument 113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize() 114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize() 118 l2addrsize(struct layer2 *l2) in l2addrsize() argument 120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize() [all …]
D	tei.c	1 // SPDX-License-Identifier: GPL-2.0-only 13 #define ID_REQUEST 1 39 #define DEACT_STATE_COUNT (ST_L1_ACTIV + 1) 57 #define DEACT_EVENT_COUNT (EV_DATIMER + 1) 72 struct manager mgr = fi->userdata; in da_debug() 84 printk(KERN_DEBUG "mgr(%d): %pV\n", mgr->ch.st->dev->id, &vaf); in da_debug() 92 struct manager mgr = fi->userdata; in da_activate() 94 if (fi->state == ST_L1_DEACT_PENDING) in da_activate() 95 mISDN_FsmDelTimer(&mgr->datimer, 1); in da_activate() 108 struct manager *mgr = fi->userdata; in da_deactivate() [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i… 33 "BriefDescription": "L2 cache request misses", 36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 41 "BriefDescription": "L2 cache requests", 44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", 50 "Data_LA": "1", 54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit… 60 "Data_LA": "1", 70 "Data_LA": "1", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i… 33 "BriefDescription": "L2 cache request misses", 36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", 41 "BriefDescription": "L2 cache requests", 44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", 50 "Data_LA": "1", 54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit… 60 "Data_LA": "1", 70 "Data_LA": "1", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/amdzen1/
D	cache.json	5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab… 15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache." 25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB." 30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs." 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach… 64 …ting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cro… 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/amdzen2/
D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/broadwellde/
D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 12 "CounterMask": "1", 22 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 28 "CounterMask": "1", 36 "AnyThread": "1", 38 "CounterMask": "1", 45 "BriefDescription": "Not rejected writebacks that hit L2 cache", 48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 53 "BriefDescription": "L2 cache lines filling L2", 56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/amdzen3/
D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/haswellx/
D	cache.json	12 "CounterMask": "1", 22 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur… 28 "CounterMask": "1", 35 "AnyThread": "1", 37 "CounterMask": "1", 51 "BriefDescription": "Not rejected writebacks that hit L2 cache", 54 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 59 "BriefDescription": "L2 cache lines filling L2", 62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2… 67 "BriefDescription": "L2 cache lines in E state filling L2", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/haswell/
D	cache.json	12 "CounterMask": "1", 22 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur… 28 "CounterMask": "1", 35 "AnyThread": "1", 37 "CounterMask": "1", 51 "BriefDescription": "Not rejected writebacks that hit L2 cache", 54 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 59 "BriefDescription": "L2 cache lines filling L2", 62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2… 67 "BriefDescription": "L2 cache lines in E state filling L2", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/tigerlake/
D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 20 "CounterMask": "1", 21 "EdgeDetect": "1", 29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 40 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 46 "CounterMask": "1", 54 "BriefDescription": "L2 cache lines filling L2", 57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 62 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/ivybridge/
D	cache.json	12 "CounterMask": "1", 23 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur… 29 "CounterMask": "1", 36 "AnyThread": "1", 38 "CounterMask": "1", 46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/broadwellx/
D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 12 "CounterMask": "1", 22 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 28 "CounterMask": "1", 36 "AnyThread": "1", 38 "CounterMask": "1", 45 "BriefDescription": "Not rejected writebacks that hit L2 cache", 48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", 53 "BriefDescription": "L2 cache lines filling L2", 56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/ivytown/
D	cache.json	12 "CounterMask": "1", 23 …rements the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occur… 29 "CounterMask": "1", 36 "AnyThread": "1", 38 "CounterMask": "1", 46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	cache.json	13 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 27 "CounterMask": "1", 28 "EdgeDetect": "1", 37 "Deprecated": "1", 44 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 47 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 55 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 61 "CounterMask": "1", 69 "BriefDescription": "L2 cache lines filling L2", 72 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/emeraldrapids/
D	cache.json	13 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 27 "CounterMask": "1", 28 "EdgeDetect": "1", 37 "Deprecated": "1", 44 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 47 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 55 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 61 "CounterMask": "1", 69 "BriefDescription": "L2 cache lines filling L2", 72 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/rocketlake/
D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 20 "CounterMask": "1", 21 "EdgeDetect": "1", 29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 40 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 46 "CounterMask": "1", 54 "BriefDescription": "L2 cache lines filling L2", 57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 62 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache… [all …]
/linux-6.8/tools/perf/pmu-events/arch/powerpc/power8/
D	cache.json	5 …essor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different… 6 …ip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads… 11 …ocessor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different… 12 …ip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads… 18 … Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1" 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …he was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetch… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 35 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load… 36 …ation other than the local core's L2 due to either only demand loads or demand loads plus prefetch… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/icelake/
D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 20 "CounterMask": "1", 21 "EdgeDetect": "1", 29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 40 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 46 "CounterMask": "1", 54 "BriefDescription": "L2 cache lines filling L2", 57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 62 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/meteorlake/
D	cache.json	14 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 30 "CounterMask": "1", 31 "EdgeDetect": "1", 40 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 43 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 52 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 59 "CounterMask": "1", 68 "BriefDescription": "L2 cache lines filling L2", 71 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 77 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/icelakex/
D	cache.json	6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 20 "CounterMask": "1", 21 "EdgeDetect": "1", 29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re… 40 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti… 46 "CounterMask": "1", 54 "BriefDescription": "L2 cache lines filling L2", 57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover … 62 …"BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", [all …]
/linux-6.8/Documentation/devicetree/bindings/cache/
D	baikal,bt1-l2-ctl.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 L2-cache Control Block 11 - Serge Semin <fancer.lancer@gmail.com> 14 By means of the System Controller Baikal-T1 SoC exposes a few settings to 15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible 16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 17 L2-cache controller block is responsible for the tuning. Its DT node is [all …]
D	freescale-l2cache.txt	`1 Freescale L2 Cache Controller 3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 8 - compatible : Should include one of the following: 9 "fsl,b4420-l2-cache-controller" 10 "fsl,b4860-l2-cache-controller" 11 "fsl,bsc9131-l2-cache-controller" 12 "fsl,bsc9132-l2-cache-controller" 13 "fsl,c293-l2-cache-controller" 14 "fsl,mpc8536-l2-cache-controller" 15 "fsl,mpc8540-l2-cache-controller" [all …]`
/linux-6.8/tools/perf/pmu-events/arch/x86/snowridgex/
D	cache.json	3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a… 6 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L… 21 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 … 25 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 28 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request… 32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 40 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p… 43 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front … 48 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou… [all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/elkhartlake/
D	cache.json	3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a… 6 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L… 21 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 … 25 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", 28 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request… 32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe… 35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d… 40 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p… 43 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front … 48 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou… [all …]

12 3 4 5 6 7 8 9 10 >>...43