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/linux-6.8/Documentation/driver-api/media/drivers/ccs/
Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
13 # v1.1 defined in version 1.1
20 module_revision_number_major 0x0002 8
[all …]
/linux-6.8/fs/nls/
Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
31 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
32 -32, -32, -32, -32, -32, /* 060-06f */
33 -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
[all …]
/linux-6.8/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]
/linux-6.8/arch/powerpc/boot/
Dwii-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
30 bcl 20, 31, 1f
31 1:
32 mflr 8
[all …]
Dgamecube-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
29 bcl 20, 31, 1f
30 1:
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
[all …]
/linux-6.8/arch/arm/mach-davinci/
Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
26 /* Offsets of the 8 compare registers on the da830 */
46 MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
47 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
48 MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false)
49 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
50 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
[all …]
Dda850.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI DA850/OMAP-L138 chip specific setup
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
7 * Derived from: arch/arm/mach-davinci/da830.c
16 #include <linux/mfd/da8xx-cfgchip.h>
20 #include <clocksource/timer-davinci.h>
62 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
64 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
65 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
66 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
[all …]
/linux-6.8/Documentation/gpu/
Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
32 * Component 1: G
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
[all …]
/linux-6.8/arch/arm64/crypto/
Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
52 ld1 {v24.1d}, [x8]
[all …]
/linux-6.8/drivers/gpu/drm/msm/disp/
Dmdp_format.c1 // SPDX-License-Identifier: GPL-2.0-only
84 * Note: Keep RGB formats 1st, followed by YUV formats to avoid breaking
89 FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
91 FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
93 FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
95 FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
97 FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
99 FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
101 FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
103 FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
[all …]
/linux-6.8/drivers/interconnect/qcom/
Dmsm8974.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
15 * |----------+-----------------------------------+-----------|
19 * |------------+-+-----------| |------------+-+-----------|
23 * |--------------+-+---------------------------------+-+-------------|
27 * |------------+-------------| |------------+-------------|
30 #include <dt-bindings/interconnect/qcom,msm8974.h>
35 #include <linux/interconnect-provider.h>
42 #include "icc-rpm.h"
45 MSM8974_BIMC_MAS_AMPSS_M0 = 1,
[all …]
/linux-6.8/drivers/media/usb/dvb-usb/
Daf9005.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header-file of the Linux driver for the Afatech 9005
3 * USB1.1 DVB-T receiver.
9 * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
15 #include "dvb-usb.h"
37 #define AF9005_TUNER_REG 1
62 #define reg_aagc_inverted_agc_len 1
65 #define reg_aagc_sign_only_pos 1
66 #define reg_aagc_sign_only_len 1
70 #define reg_aagc_slow_adc_en_len 1
[all …]
/linux-6.8/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
Dramcfg.h1 /* SPDX-License-Identifier: MIT */
11 unsigned rammap_00_16_20:1;
12 unsigned rammap_00_16_40:1;
13 unsigned rammap_00_17_02:1;
16 unsigned rammap_10_04_02:1;
17 unsigned rammap_10_04_08:1;
20 unsigned rammap_11_08_01:1;
22 unsigned rammap_11_08_10:1;
25 unsigned rammap_11_0a_0400:1;
26 unsigned rammap_11_0a_0800:1;
[all …]
/linux-6.8/arch/arc/include/asm/
Darcregs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
16 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
56 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
57 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
58 #define STATUS_U_MASK (1<<STATUS_U_BIT)
59 #define STATUS_Z_MASK (1<<STATUS_Z_BIT)
60 #define STATUS_L_MASK (1<<STATUS_L_BIT)
63 * ECR: Exception Cause Reg bits-n-pieces
65 * [15: 8] = Exception Cause Code
[all …]
/linux-6.8/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2014 Tensilica Inc.
36 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
44 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
45 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
49 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
54 #define XCHAL_CP0_SA_ALIGN 1
56 #define XCHAL_CP2_SA_ALIGN 1
58 #define XCHAL_CP3_SA_ALIGN 1
60 #define XCHAL_CP4_SA_ALIGN 1
[all …]
/linux-6.8/include/sound/
Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
30 UMP_CC_MODULATION = 1,
36 UMP_CC_BALANCE = 8,
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
154 u32 note:8;
155 u32 data:8;
157 u32 data:8;
[all …]
/linux-6.8/drivers/pinctrl/uniphier/
Dpinctrl-uniphier-pxs2.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2015-2017 Socionext Inc.
12 #include "pinctrl-uniphier.h"
18 UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
19 1, UNIPHIER_PIN_DRV_1BIT,
20 1, UNIPHIER_PIN_PULL_DOWN),
39 UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
40 8, UNIPHIER_PIN_DRV_1BIT,
41 8, UNIPHIER_PIN_PULL_DOWN),
61 -1, UNIPHIER_PIN_DRV_FIXED8,
[all …]
/linux-6.8/drivers/media/test-drivers/vicodec/
Dcodec-fwht.c1 // SPDX-License-Identifier: LGPL-2.1+
6 * 8x8 Fast Walsh Hadamard Transform in sequency order based on the paper:
8 * A Recursive Algorithm for Sequency-Ordered Fast Walsh Transforms,
15 #include "codec-fwht.h"
21 * be guaranteed that the magic 8 byte sequence (see below) can
28 #define IBLOCK 1
34 1, 8,
57 s16 block[8 * 8]; in rlc()
67 for (y = 0; y < 8; y++) { in rlc()
68 for (x = 0; x < 8; x++) { in rlc()
[all …]
/linux-6.8/drivers/gpu/drm/vmwgfx/device_include/
Dsvga3d_surfacedefs.h2 * Copyright 2008-2021 VMware, Inc.
3 * SPDX-License-Identifier: GPL-2.0 OR MIT
28 * svga3d_surfacedefs.h --
57 SVGA3DBLOCKDESC_BLUE = 1 << 0,
58 SVGA3DBLOCKDESC_W = 1 << 0,
59 SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
61 SVGA3DBLOCKDESC_GREEN = 1 << 1,
62 SVGA3DBLOCKDESC_V = 1 << 1,
64 SVGA3DBLOCKDESC_RED = 1 << 2,
65 SVGA3DBLOCKDESC_U = 1 << 2,
[all …]
/linux-6.8/arch/alpha/lib/
Dev6-memcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memcpy.S
4 * 21264 version by Rick Gorton <rick.gorton@alpha-processor.com>
8 * - memory accessed as aligned quadwords only
9 * - uses bcmpge to compare 8 bytes in parallel
14 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
16 * E - either cluster
17 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
21 * $1,$2, - scratch
[all …]
/linux-6.8/drivers/pinctrl/mediatek/
Dpinctrl-mt8173.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
15 #include "pinctrl-mtk-common.h"
16 #include "pinctrl-mtk-mt8173.h"
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
[all …]
/linux-6.8/drivers/input/misc/
Dyealink.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 u8 size; /* 1-11, size of used data bytes. */
38 * size 1
48 * size 1
49 * offset key number [0-1f]
57 * size 1-11
58 * offset 0-23
66 * size 1
68 * data[0] 0 OFF / 1 ON
75 * size 1
[all …]
/linux-6.8/include/asm-generic/
Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-generic/xor.h
5 * Generic optimized RAID-5 checksumming functions.
14 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_2()
18 p1[1] ^= p2[1]; in xor_8regs_2()
25 p1 += 8; in xor_8regs_2()
26 p2 += 8; in xor_8regs_2()
27 } while (--lines > 0); in xor_8regs_2()
35 long lines = bytes / (sizeof (long)) / 8; in xor_8regs_3()
39 p1[1] ^= p2[1] ^ p3[1]; in xor_8regs_3()
[all …]
/linux-6.8/arch/x86/lib/
Dmemmove_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
4 * of line code. Based on asm-i386/string.h.
6 * This assembly file is re-written from memmove_64.c file.
7 * - Copyright 2011 Fenghua Yu <fenghua.yu@intel.com>
41 #define CHECK_LEN cmp $0x20, %rdx; jb 1f
67 movq 0*8(%rsi), %r11
68 movq 1*8(%rsi), %r10
69 movq 2*8(%rsi), %r9
70 movq 3*8(%rsi), %r8
71 leaq 4*8(%rsi), %rsi
[all …]
/linux-6.8/drivers/gpu/drm/i915/gt/shaders/clear_kernel/
Divb.asm1 // SPDX-License-Identifier: MIT
9 * 1. Clear all 64 GRF registers assigned to the kernel with designated value;
15 mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N };
20 * DW 1.0 - Block Offset to write Render Cache
21 * DW 1.1 [15:0] - Clear Word
22 * DW 1.2 - Delay iterations
23 * DW 1.3 - Enable Instrumentation (only for debug)
24 * DW 1.4 - Rsvd (intended for context ID)
25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
[all …]

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