| /linux-5.10/arch/parisc/kernel/ |
| D | perf_images.h | 27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
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| /linux-5.10/net/netfilter/ipset/ |
| D | pfxlen.c | 12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
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| /linux-5.10/drivers/gpu/drm/radeon/ |
| D | btc_dpm.c | 36 #define MC_CG_ARB_FREQ_F0 0x0a
37 #define MC_CG_ARB_FREQ_F1 0x0b
38 #define MC_CG_ARB_FREQ_F2 0x0c
39 #define MC_CG_ARB_FREQ_F3 0x0d
41 #define MC_CG_SEQ_DRAMCONF_S0 0x05
42 #define MC_CG_SEQ_DRAMCONF_S1 0x06
43 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
44 #define MC_CG_SEQ_YCLK_RESUME 0x0a
46 #define SMC_RAM_END 0x8000
61 0x000008f8, 0x00000010, 0xffffffff,
[all …]
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| D | rv770.c | 53 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
68 return 0; in rv770_set_uvd_clocks()
72 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
81 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
82 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
87 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
114 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
118 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
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| D | ni_dpm.c | 35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
40 #define SMC_RAM_END 0xC000
44 0x15,
45 0x2,
46 0x19,
47 0x2,
48 0x8,
[all …]
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| D | evergreen.c | 42 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
43 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
44 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
55 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
66 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
77 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
88 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
99 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
110 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
129 0x98fc,
[all …]
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| /linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/ |
| D | tpc0_cfg_masks.h | 23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
[all …]
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| D | dma_ch_0_masks.h | 23 #define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_SHIFT 0
24 #define DMA_CH_0_CFG0_RD_MAX_OUTSTAND_MASK 0x3FF
26 #define DMA_CH_0_CFG0_WR_MAX_OUTSTAND_MASK 0xFFF0000
29 #define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_SHIFT 0
30 #define DMA_CH_0_CFG1_RD_BUF_MAX_SIZE_MASK 0x3FF
33 #define DMA_CH_0_ERRMSG_ADDR_LO_VAL_SHIFT 0
34 #define DMA_CH_0_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF
37 #define DMA_CH_0_ERRMSG_ADDR_HI_VAL_SHIFT 0
38 #define DMA_CH_0_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF
41 #define DMA_CH_0_ERRMSG_WDATA_VAL_SHIFT 0
[all …]
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| D | mme_masks.h | 23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
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| /linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/ |
| D | tpc0_cfg_masks.h | 23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
[all …]
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| D | dma0_core_masks.h | 23 #define DMA0_CORE_CFG_0_EN_SHIFT 0
24 #define DMA0_CORE_CFG_0_EN_MASK 0x1
27 #define DMA0_CORE_CFG_1_HALT_SHIFT 0
28 #define DMA0_CORE_CFG_1_HALT_MASK 0x1
30 #define DMA0_CORE_CFG_1_FLUSH_MASK 0x2
32 #define DMA0_CORE_CFG_1_SB_FORCE_MISS_MASK 0x4
35 #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_SHIFT 0
36 #define DMA0_CORE_LBW_MAX_OUTSTAND_VAL_MASK 0x1F
39 #define DMA0_CORE_SRC_BASE_LO_VAL_SHIFT 0
40 #define DMA0_CORE_SRC_BASE_LO_VAL_MASK 0xFFFFFFFF
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | smu_11_0_cdr_table.h | 36 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x0…
37 0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x0…
38 0x0f0f0f0f, 0xf0f00f0f, 0x0f0ff0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf…
39 0xf0f00f0f, 0x0f0ff0f0, 0x0f0ff0f0, 0xf0f0f0f0, 0x0f0ff0f0, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0x0…
46 0xffffffff, 0xffffffff, 0xffffffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0xf…
47 0xffffffff, 0x0000ffff, 0x00000000, 0xffffffff, 0x00000000, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xf…
48 0xffffffff, 0x0000ffff, 0xffff0000, 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x0000ffff, 0x0…
49 0x0000ffff, 0xffff0000, 0xffff0000, 0x00000000, 0xffff0000, 0x00000000, 0xffffffff, 0x00000000, 0xf…
57 …0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f00f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0x…
58 …0x0f0f0f0f, 0xf0f00f0f, 0xf0f0f0f0, 0x0f0f0f0f, 0xf0f0f0f0, 0xf0f00f0f, 0xf0f00f0f, 0xf0f00f0f, 0x…
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | si.c | 59 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011,
60 mmCB_HW_CONTROL, 0x00010000, 0x00018208,
61 mmDB_DEBUG, 0xffffffff, 0x00000000,
62 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
63 mmDB_DEBUG3, 0x0002021c, 0x00020200,
64 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
65 0x340c, 0x000000c0, 0x00800040,
66 0x360c, 0x000000c0, 0x00800040,
67 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
68 mmFBC_MISC, 0x00200000, 0x50100000,
[all …]
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| D | mxgpu_vi.c | 47 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
48 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
49 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
50 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
51 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
52 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
53 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
54 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
55 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
56 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
[all …]
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| D | cik.c | 129 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_rreg()
140 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); in cik_uvd_ctx_wreg()
169 0xc200, 0xe0ffffff, 0xe0000000
174 0x31dc, 0xffffffff, 0x00000800,
175 0x31dd, 0xffffffff, 0x00000800,
176 0x31e6, 0xffffffff, 0x00007fbf,
177 0x31e7, 0xffffffff, 0x00007faf
182 0xcd5, 0x00000333, 0x00000333,
183 0xcd4, 0x000c0fc0, 0x00040200,
184 0x2684, 0x00010000, 0x00058208,
[all …]
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| D | gfx_v10_0.c | 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
64 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
71 …R_CONFIG__NUM_PKRS__SHIFT 0x8
72 …__NUM_PKRS_MASK 0x00000700L
74 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
76 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_7_0_1_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
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| D | smu_7_1_0_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
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| D | smu_7_1_1_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
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| D | smu_7_1_2_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
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| D | smu_7_1_3_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
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| D | smu_7_0_0_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
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| D | smu_8_0_sh_mask.h | 27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
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| /linux-5.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
| D | mmhub_2_0_0_default.h | 26 #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
27 #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
28 #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
29 #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
30 #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
31 #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
32 #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
33 #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
34 #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
35 #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
[all …]
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| /linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/ |
| D | table.c | 7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]
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