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/linux-5.10/arch/arm/mach-mv78xx0/
Dmv78xx0.h20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
/linux-5.10/arch/arm/mach-mmp/
Daddr-map.h15 #define APB_PHYS_BASE 0xd4000000
16 #define APB_VIRT_BASE IOMEM(0xfe000000)
17 #define APB_PHYS_SIZE 0x00200000
19 #define AXI_PHYS_BASE 0xd4200000
20 #define AXI_VIRT_BASE IOMEM(0xfe200000)
21 #define AXI_PHYS_SIZE 0x00200000
23 #define PGU_PHYS_BASE 0xe0000000
24 #define PGU_VIRT_BASE IOMEM(0xfe400000)
25 #define PGU_PHYS_SIZE 0x00100000
27 /* Static Memory Controller - Chip Select 0 and 1 */
[all …]
/linux-5.10/arch/arm/include/debug/
Dsti.S9 #define STIH41X_COMMS_BASE 0xfed00000
10 #define STIH41X_ASC2_BASE (STIH41X_COMMS_BASE+0x32000)
12 #define STIH41X_SBC_LPM_BASE 0xfe400000
13 #define STIH41X_SBC_COMMS_BASE (STIH41X_SBC_LPM_BASE + 0x100000)
14 #define STIH41X_SBC_ASC1_BASE (STIH41X_SBC_COMMS_BASE + 0x31000)
17 #define VIRT_ADDRESS(x) (x - 0x1000000)
31 #define ASC_TX_BUF_OFF 0x04
32 #define ASC_CTRL_OFF 0x0c
33 #define ASC_STA_OFF 0x14
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Drenesas,dbsc.yaml51 reg = <0xfe400000 0x400>;
/linux-5.10/arch/arm/mach-tegra/
Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/linux-5.10/arch/arm/mach-dove/
Ddove.h19 * e0000000 @runtime 128M PCIe-0 Memory space
23 * f2000000 fee00000 1M PCIe-0 I/O space
27 #define DOVE_CESA_PHYS_BASE 0xc8000000
28 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
31 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
34 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
37 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
40 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
44 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/linux-5.10/arch/powerpc/boot/dts/fsl/
Dgef_sbc310.dts25 reg = <0x0 0x40000000>; // set by uboot
29 reg = <0xfef05000 0x1000>;
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
34 3 0 0xfc100000 0x00020000 // NVRAM
35 4 0 0xfc000000 0x00010000>; // FPGA
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
38 flash@0,0 {
40 reg = <0x0 0x0 0x01000000>;
[all …]
/linux-5.10/arch/arm/probes/
Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]
/linux-5.10/arch/arm/boot/dts/
Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
[all …]
Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
/linux-5.10/arch/sparc/mm/
Dsrmmu.c107 { return !(pmd_val(pmd) & 0xFFFFFFF); } in srmmu_pmd_none()
121 #define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
126 #define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
130 __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t" in msi_set_sync()
132 "sta %%g3, [%0] %1\n\t" : : in msi_set_sync()
154 printk(KERN_ERR "Size 0x%x too small for nocache request\n", in __srmmu_get_nocache()
159 printk(KERN_ERR "Size 0x%x unaligned in nocache request\n", in __srmmu_get_nocache()
186 memset(tmp, 0, size); in srmmu_get_nocache()
198 printk("Vaddr %lx is smaller than nocache base 0x%lx\n", in srmmu_free_nocache()
203 printk("Vaddr %lx is bigger than nocache end 0x%lx\n", in srmmu_free_nocache()
[all …]