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/linux-5.10/Documentation/devicetree/bindings/timer/ !
Darm,arch_timer_mmio.yaml63 '^frame@[0-9a-z]*$':
69 minimum: 0
105 ranges = <0 0xf0001000 0x1000>;
106 reg = <0xf0000000 0x1000>;
109 frame@0 {
110 frame-number = <0>;
111 interrupts = <0 13 0x8>,
112 <0 14 0x8>;
113 reg = <0x0000 0x1000>,
114 <0x1000 0x1000>;
[all …]
/linux-5.10/arch/arm/mach-mmp/ !
Dregs-usb.h9 #define PXA168_U2O_REGBASE (0xd4208000)
10 #define PXA168_U2O_PHYBASE (0xd4207000)
12 #define PXA168_U2H_REGBASE (0xd4209000)
13 #define PXA168_U2H_PHYBASE (0xd4206000)
15 #define MMP3_HSIC1_REGBASE (0xf0001000)
16 #define MMP3_HSIC1_PHYBASE (0xf0001800)
18 #define MMP3_HSIC2_REGBASE (0xf0002000)
19 #define MMP3_HSIC2_PHYBASE (0xf0002800)
21 #define MMP3_FSIC_REGBASE (0xf0003000)
22 #define MMP3_FSIC_PHYBASE (0xf0003800)
[all …]
/linux-5.10/arch/arc/plat-axs10x/ !
Daxs10x.c17 #define AXS_MB_CGU 0xE0010000
18 #define AXS_MB_CREG 0xE0011000
20 #define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214)
21 #define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220)
22 #define CREG_MB_VER (AXS_MB_CREG + 0x230)
23 #define CREG_MB_CONFIG (AXS_MB_CREG + 0x234)
25 #define AXC001_CREG 0xF0001000
26 #define AXC001_GPIO_INTC 0xF0003000
62 #define GPIO_INTEN (AXC001_GPIO_INTC + 0x30) in axs10x_enable_gpio_intc_wire()
63 #define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34) in axs10x_enable_gpio_intc_wire()
[all …]
/linux-5.10/arch/arm/boot/dts/ !
Dmmp3.dtsi16 #size-cells = <0>;
19 cpu@0 {
23 reg = <0>;
45 reg = <0xd4200000 0x00200000>;
52 reg = <0xd4282000 0x1000>,
53 <0xd4284000 0x100>;
62 reg = <0x150 0x4>, <0x168 0x4>;
72 reg = <0x154 0x4>, <0x16c 0x4>;
82 reg = <0x1bc 0x4>, <0x1a4 0x4>;
92 reg = <0x1c0 0x4>, <0x1a8 0x4>;
[all …]
Dr8a7779.dtsi22 #size-cells = <0>;
24 cpu@0 {
27 reg = <0>;
67 reg = <0xf0001000 0x1000>,
68 <0xf0000100 0x100>;
73 reg = <0xf0000200 0x100>;
81 reg = <0xf0000600 0x20>;
89 reg = <0xffc40000 0x2c>;
93 gpio-ranges = <&pfc 0 0 32>;
100 reg = <0xffc41000 0x2c>;
[all …]
Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]