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/linux/drivers/clk/hisilicon/
H A Dclk-hi3519.c35 { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
36 { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
37 { HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
38 { HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
39 { HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
40 { HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
41 { HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
42 { HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
43 { HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
48 static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
[all …]
H A Dcrg-hi3516cv300.c40 { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
41 { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
42 { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
43 { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
44 { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
45 { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
46 { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
47 { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
48 { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
49 { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-eth.c18 .set_ofs = 0xe4,
19 .clr_ofs = 0xe4,
20 .sta_ofs = 0xe4,
34 .set_ofs = 0xe4,
35 .clr_ofs = 0xe4,
36 .sta_ofs = 0xe4,
50 .set_ofs = 0x30,
51 .clr_ofs = 0x30,
52 .sta_ofs = 0x30,
H A Dclk-mt7981-eth.c20 .set_ofs = 0xE4,
21 .clr_ofs = 0xE4,
22 .sta_ofs = 0xE4,
42 .set_ofs = 0xE4,
43 .clr_ofs = 0xE4,
44 .sta_ofs = 0xE4,
64 .set_ofs = 0x30,
65 .clr_ofs = 0x30,
66 .sta_ofs = 0x30,
H A Dclk-mt7622-eth.c21 .set_ofs = 0x30,
22 .clr_ofs = 0x30,
23 .sta_ofs = 0x30,
35 .set_ofs = 0xE4,
36 .clr_ofs = 0xE4,
37 .sta_ofs = 0xE4,
54 static u16 rst_ofs[] = { 0x34, };
H A Dclk-mt7988-eth.c20 .set_ofs = 0x30,
21 .clr_ofs = 0x30,
22 .sta_ofs = 0x30,
36 GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
53 .set_ofs = 0xe4,
54 .clr_ofs = 0xe4,
55 .sta_ofs = 0xe4,
89 .set_ofs = 0x14,
90 .clr_ofs = 0x14,
91 .sta_ofs = 0x14,
[all …]
H A Dclk-mt7629-eth.c21 .set_ofs = 0x30,
22 .clr_ofs = 0x30,
23 .sta_ofs = 0x30,
35 .set_ofs = 0xE4,
36 .clr_ofs = 0xE4,
37 .sta_ofs = 0xE4,
65 static u16 rst_ofs[] = { 0x34, };
/linux/crypto/
H A Dtestmgr.h34 * @ksize: Length of @key in bytes (0 if no key)
101 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
229 "\x63\x1c\xcd\x7b\xe1\x7e\xe4\xde\xc9\xa8\x89\xa1\x74\xcb\x3c\x63"
230 "\x7d\x24\xec\x83\xc3\x15\xe4\x7f\x73\x05\x34\xd1\xec\x22\xbb\x8a"
259 "\xAF\x94\x28\xC2\xB7\xB8\x88\x3F\xE4\x46\x3A\x4B\xC8\x5B\x1C\xB3"
274 "\x54\x49\x4C\xA6\x3E\xBA\x03\x37\xE4\xE2\x40\x23\xFC\xD6\x9A\x5A"
281 "\xF9\x80\x3F\x8F\x6F\x8A\xE3\x42\xE9\x31\xFD\x8A\xE4\x7A\x22\x0D"
311 "\x41\xE4\x25\x99\xAC\xFC\xD2\x0F\x02\xD3\xD1\x54\x06\x1A\x51\x77"
314 "\x8C\x33\xE4\x36\xB8\x43\xEB\x19\x2A\x81\x8D\xDE\x81\x0A\x99\x48"
331 "\xEF\x7F\x60\xE4\xE6\x05\x82\x89\x5D\xDF\xC6\xD2\x6C\x07\x91\x33"
[all …]
H A Dhkdf.c41 * Returns 0 on success with the pseudorandom key stored in @prk,
71 * Returns 0 on success with output keying material stored in @okm,
90 for (i = 0; i < okmlen; i += hashlen) { in hkdf_expand()
122 err = 0; in hkdf_expand()
186 "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef"
205 .salt_size = 0,
207 .info_size = 0,
239 .info_size = 0,
266 "\x48\xb6\x45\x77\x63\xe4\xf0\x20\x4f\xc5",
285 "\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef"
[all …]
H A Ddh.c27 memset(ctx, 0, sizeof(*ctx)); in dh_clear_ctx()
50 return (p_len < 2048) ? -EINVAL : 0; in dh_check_params_length()
52 return (p_len < 1536) ? -EINVAL : 0; in dh_check_params_length()
68 return 0; in dh_set_params()
80 if (crypto_dh_decode_key(buf, len, &params) < 0) in dh_set_secret()
83 if (dh_set_params(ctx, &params) < 0) in dh_set_secret()
90 return 0; in dh_set_secret()
113 return 0; in dh_is_pubkey_valid()
126 if (mpi_cmp_ui(y, 1) < 1 || mpi_cmp(y, ctx->p) >= 0) in dh_is_pubkey_valid()
134 val = mpi_alloc(0); in dh_is_pubkey_valid()
[all …]
/linux/drivers/char/
H A Dtoshiba.c11 * 0xfc02: Scott Eisert <scott.e@sky-eye.com>
12 * 0xfc04: Steve VanDevender <stevev@efn.org>
13 * 0xfc08: Garth Berry <garth@itsbruce.net>
14 * 0xfc0a: Egbert Eich <eich@xfree86.org>
15 * 0xfc10: Andrew Lofthouse <Andrew.Lofthouse@robins.af.mil>
16 * 0xfc11: Spencer Olson <solson@novell.com>
17 * 0xfc13: Claudius Frankewitz <kryp@gmx.de>
18 * 0xfc15: Tom May <tom@you-bastards.com>
19 * 0xfc17: Dave Konrad <konrad@xenia.it>
20 * 0xfc1a: George Betzos <betzos@engr.colostate.edu>
[all …]
/linux/drivers/media/dvb-frontends/
H A Ds5h1432.c40 } while (0)
48 struct i2c_msg msg = {.addr = addr, .flags = 0, .buf = buf, .len = 2 }; in s5h1432_writereg()
53 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n", in s5h1432_writereg()
56 return (ret != 1) ? -1 : 0; in s5h1432_writereg()
63 u8 b1[] = { 0 }; in s5h1432_readreg()
66 {.addr = addr, .flags = 0, .buf = b0, .len = 1}, in s5h1432_readreg()
75 return b1[0]; in s5h1432_readreg()
80 return 0; in s5h1432_sleep()
88 u8 reg = 0; in s5h1432_set_channel_bandwidth()
90 /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */ in s5h1432_set_channel_bandwidth()
[all …]
/linux/fs/nls/
H A Dnls_euc-jp.c17 #define IS_SJIS_LOW_BYTE(l) ((0x40 <= (l)) && ((l) <= 0xFC) && ((l) != 0x7F))
19 #define IS_SJIS_JISX0208(h, l) ((((0x81 <= (h)) && ((h) <= 0x9F)) \
20 || ((0xE0 <= (h)) && ((h) <= 0xEA))) \
22 #define IS_SJIS_JISX0201KANA(c) ((0xA1 <= (c)) && ((c) <= 0xDF))
23 #define IS_SJIS_UDC_LOW(h, l) (((0xF0 <= (h)) && ((h) <= 0xF4)) \
25 #define IS_SJIS_UDC_HI(h, l) (((0xF5 <= (h)) && ((h) <= 0xF9)) \
27 #define IS_SJIS_IBM(h, l) (((0xFA <= (h)) && ((h) <= 0xFC)) \
29 #define IS_SJIS_NECIBM(h, l) (((0xED <= (h)) && ((h) <= 0xEE)) \
32 if ((sjis_lo) >= 0x9F) { \
37 (euc_lo) = (sjis_lo) + ((sjis_lo) >= 0x7F ? 0x60 : 0x61); \
[all …]
/linux/lib/crypto/tests/
H A Dsha512-testvecs.h9 .data_len = 0,
11 0xcf, 0x83, 0xe1, 0x35, 0x7e, 0xef, 0xb8, 0xbd,
12 0xf1, 0x54, 0x28, 0x50, 0xd6, 0x6d, 0x80, 0x07,
13 0xd6, 0x20, 0xe4, 0x05, 0x0b, 0x57, 0x15, 0xdc,
14 0x83, 0xf4, 0xa9, 0x21, 0xd3, 0x6c, 0xe9, 0xce,
15 0x47, 0xd0, 0xd1, 0x3c, 0x5d, 0x85, 0xf2, 0xb0,
16 0xff, 0x83, 0x18, 0xd2, 0x87, 0x7e, 0xec, 0x2f,
17 0x63, 0xb9, 0x31, 0xbd, 0x47, 0x41, 0x7a, 0x81,
18 0xa5, 0x38, 0x32, 0x7a, 0xf9, 0x27, 0xda, 0x3e,
24 0x12, 0xf2, 0xb6, 0xec, 0x84, 0xa0, 0x8e, 0xcf,
[all …]
H A Dsha256-testvecs.h9 .data_len = 0,
11 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
12 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
13 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
14 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55,
20 0x45, 0xf8, 0x3d, 0x17, 0xe1, 0x0b, 0x34, 0xfc,
21 0xa0, 0x1e, 0xb8, 0xf4, 0x45, 0x4d, 0xac, 0x34,
22 0xa7, 0x77, 0xd9, 0x40, 0x4a, 0x46, 0x4e, 0x73,
23 0x2c, 0xf4, 0xab, 0xf2, 0xc0, 0xda, 0x94, 0xc4,
29 0xf9, 0xd3, 0x52, 0x2f, 0xd5, 0xe0, 0x99, 0x15,
[all …]
H A Dsha1-testvecs.h9 .data_len = 0,
11 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
12 0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90,
13 0xaf, 0xd8, 0x07, 0x09,
19 0x0a, 0xd0, 0x52, 0xdd, 0x9f, 0x32, 0x40, 0x55,
20 0x21, 0xe4, 0x3c, 0x6e, 0xbd, 0xc5, 0x2f, 0x5a,
21 0x02, 0x54, 0x93, 0xb2,
27 0x13, 0x83, 0x82, 0x03, 0x23, 0xff, 0x46, 0xd6,
28 0x12, 0x7f, 0xad, 0x05, 0x2b, 0xc3, 0x4a, 0x42,
29 0x49, 0x6a, 0xf8, 0x84,
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-m53menlo.dts15 pinctrl-0 = <&pinctrl_power_button>;
27 pinctrl-0 = <&pinctrl_power_out>;
35 pinctrl-0 = <&pinctrl_led>;
61 #size-cells = <0>;
63 port@0 {
64 reg = <0>;
84 pinctrl-0 = <&pinctrl_display_gpio>;
86 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
97 pinctrl-0 = <&pinctrl_beeper>;
106 gpio = <&gpio1 2 0>;
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-magnachip-d53e6ea8966.c74 #define MCS_ELVSS_ON 0xb1
75 #define MCS_TEMP_SWIRE 0xb2
76 #define MCS_PASSWORD_0 0xf0
77 #define MCS_PASSWORD_1 0xf1
78 #define MCS_ANALOG_PWR_CTL_0 0xf4
79 #define MCS_ANALOG_PWR_CTL_1 0xf5
80 #define MCS_GTCON_SET 0xf7
81 #define MCS_GATELESS_SIGNAL_SET 0xf8
82 #define MCS_SET_GAMMA 0xf9
91 {0x01, 0x79, 0x78, 0x8d, 0xd9, 0xdf, 0xd5, 0xcb, 0xcf, 0xc5,
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-regs.h11 * locates in one single space starts from 0 but in different sctions with
12 * different addresses, the subsystem offsets are defined to 0 as the
13 * register definition will have the address offset to 0.
15 #define IPU6_UNIFIED_OFFSET 0
17 #define IPU6_ISYS_IOMMU0_OFFSET 0x2e0000
18 #define IPU6_ISYS_IOMMU1_OFFSET 0x2e0500
19 #define IPU6_ISYS_IOMMUI_OFFSET 0x2e0a00
21 #define IPU6_PSYS_IOMMU0_OFFSET 0x1b0000
22 #define IPU6_PSYS_IOMMU1_OFFSET 0x1b0700
23 #define IPU6_PSYS_IOMMU1R_OFFSET 0x1b0e00
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dbrcm,misc.yaml49 reg = <0xff802600 0xe4>;
53 ranges = <0x0 0x0 0xe4>;
57 reg = <0x44 0x4>;
/linux/drivers/scsi/
H A Dscsi_proto_test.c14 } d = { .arr = { 0x45, 0, 0, 0, 0xb0, 0xe4, 0xe3 } }; in test_scsi_proto()
15 KUNIT_EXPECT_EQ(test, d.desc.io_advice_hints_mode + 0, 1); in test_scsi_proto()
16 KUNIT_EXPECT_EQ(test, d.desc.st_enble + 0, 1); in test_scsi_proto()
17 KUNIT_EXPECT_EQ(test, d.desc.cs_enble + 0, 0); in test_scsi_proto()
18 KUNIT_EXPECT_EQ(test, d.desc.ic_enable + 0, 1); in test_scsi_proto()
19 KUNIT_EXPECT_EQ(test, d.desc.acdlu + 0, 1); in test_scsi_proto()
20 KUNIT_EXPECT_EQ(test, d.desc.rlbsr + 0, 3); in test_scsi_proto()
21 KUNIT_EXPECT_EQ(test, d.desc.lbm_descriptor_type + 0, 0); in test_scsi_proto()
22 KUNIT_EXPECT_EQ(test, d.desc.params[0] + 0, 0xe4); in test_scsi_proto()
23 KUNIT_EXPECT_EQ(test, d.desc.params[1] + 0, 0xe3); in test_scsi_proto()
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
H A Dkeystone-reset.txt32 in format: <0>, <2>; It can be in random order and
33 begins from 0 to 3, as keystone can contain up to 4 SoC
42 reg = <0x02310000 0x200>;
47 reg = <0x02620000 0x1000>;
52 ti,syscon-pll = <&pllctrl 0xe4>;
53 ti,syscon-dev = <&devctrl 0x328>;
54 ti,wdt-list = <0>;
63 ti,syscon-pll = <&pllctrl 0xe4>;
64 ti,syscon-dev = <&devctrl 0x328>;
65 ti,wdt-list = <0>, <2>;
/linux/lib/crypto/
H A Daescfb.c47 while (len > 0) { in aescfb_encrypt()
75 aescfb_encrypt_block(ctx, ks[0], iv); in aescfb_decrypt()
77 for (int i = 0; len > 0; i ^= 1) { in aescfb_decrypt()
127 "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
151 "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
176 "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
187 "\x20\x31\x62\x3d\x55\xb1\xe4\x71",
216 for (int i = 0; i < ARRAY_SIZE(aescfb_tv); i++) { in libaescfb_init()
248 return 0; in libaescfb_init()
/linux/drivers/net/wireless/intersil/p54/
H A Dp54spi_eeprom.h19 0x47, 0x4d, 0x55, 0xaa, /* magic */
20 0x00, 0x00, /* pad */
21 0x00, 0x00, /* eeprom_pda_data_wrap length */
22 0x00, 0x00, 0x00, 0x00, /* arm opcode */
25 0x04, 0x00, 0x01, 0x01, /* PDR_MAC_ADDRESS */
26 0x00, 0x02, 0xee, 0xc0, 0xff, 0xee,
29 0x06, 0x00, 0x01, 0x10, /* PDR_INTERFACE_LIST */
30 0x00, 0x00, /* role */
31 0x0f, 0x00, /* if_id */
32 0x85, 0x00, /* variant = Longbow RF, 2GHz */
[all …]
/linux/drivers/ufs/host/
H A Dufs-hisi.h14 #define PSW_POWER_CTRL (0x04)
15 #define PHY_ISO_EN (0x08)
16 #define HC_LP_CTRL (0x0C)
17 #define PHY_CLK_CTRL (0x10)
18 #define PSW_CLK_CTRL (0x14)
19 #define CLOCK_GATE_BYPASS (0x18)
20 #define RESET_CTRL_EN (0x1C)
21 #define UFS_SYSCTRL (0x5C)
22 #define UFS_DEVICE_RESET_CTRL (0x60)
25 #define BIT_UFS_PSW_MTCMOS_EN (1 << 0)
[all …]

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