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/qemu/docs/system/arm/
H A Dxlnx-zynq.rst17 - SMC SRAM@0xe2000000 64MB
/qemu/docs/devel/
H A Dmemory.rst227 For example, suppose we have a container A of size 0x8000 with two subregions
228 B and C. B is a container mapped at 0x2000, size 0x4000, priority 2; C is
229 an MMIO region mapped at 0x0, size 0x6000, priority 1. B currently has two
230 of its own subregions: D of size 0x1000 at offset 0 and E of size 0x1000 at
231 offset 0x2000. As a diagram::
233 0 1000 2000 3000 4000 5000 6000 7000 8000
295 system_memory: container@0-2^48-1
297 +---- lomem: alias@0-0xdfffffff ---> #ram (0-0xdfffffff)
299 +---- himem: alias@0x100000000-0x11fffffff ---> #ram (0xe0000000-0xffffffff)
301 +---- vga-window: alias@0xa0000-0xbffff ---> #pci (0xa0000-0xbffff)
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/qemu/hw/arm/
H A Dxilinx_zynq.c57 #define MPCORE_PERIPHBASE 0xF8F00000
58 #define ZYNQ_BOARD_MIDR 0x413FC090
66 #define BOARD_SETUP_ADDR 0x100
68 #define SLCR_LOCK_OFFSET 0x004
69 #define SLCR_UNLOCK_OFFSET 0x008
70 #define SLCR_ARM_PLL_OFFSET 0x100
72 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
73 #define SLCR_XILINX_LOCK_KEY 0x767b
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
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