Searched +full:0 +full:xe10 (Results 1 – 5 of 5) sorted by relevance
/qemu/hw/misc/ |
H A D | armv7m_ras.c | 24 case 0xe10: /* ERRIIDR */ in ras_read() 25 /* architect field = Arm; product/variant/revision 0 */ in ras_read() 26 *data = 0x43b; in ras_read() 28 case 0xfc8: /* ERRDEVID */ in ras_read() 29 /* Minimal RAS: we implement 0 error record indexes */ in ras_read() 30 *data = 0; in ras_read() 33 qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", in ras_read() 35 *data = 0; in ras_read() 51 qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", in ras_write() 71 s, "armv7m-ras", 0x1000); in armv7m_ras_init()
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/qemu/include/hw/pci-host/ |
H A D | pnv_phb3_regs.h | 19 #define PBCQ_NEST_IRSN_COMPARE 0x1a 20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18) 21 #define PBCQ_NEST_IRSN_MASK 0x1b 22 #define PBCQ_NEST_LSI_SRC_ID 0x1f 23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7) 24 #define PBCQ_NEST_REGS_COUNT 0x46 25 #define PBCQ_NEST_MMIO_BAR0 0x40 26 #define PBCQ_NEST_MMIO_BAR1 0x41 27 #define PBCQ_NEST_PHB_BAR 0x42 28 #define PBCQ_NEST_MMIO_MASK0 0x43 [all …]
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H A D | pnv_phb4_regs.h | 32 * stacks, thus for PEC2, the global registers are at offset 0, the 33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc.... 36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc.. 38 #define PEC_STACK_OFFSET 0x40 41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00 42 #define PEC_NEST_DROP_PRIO_CTRL 0x01 43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02 44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03 45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04 46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05 [all …]
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/qemu/hw/net/fsl_etsec/ |
H A D | registers.h | 49 #define DMACTRL_WOP (1 << 0) 51 #define IEVENT_PERR (1 << 0) 94 #define MACCFG1_TX_EN (1 << 0) 100 #define MIIMCOM_READ (1 << 0) 103 #define RCTRL_PRSDEP_MASK (0x3) 109 #define TSEC_ID (0x000 / 4) 110 #define TSEC_ID2 (0x004 / 4) 111 #define IEVENT (0x010 / 4) 112 #define IMASK (0x014 / 4) 113 #define EDIS (0x018 / 4) [all …]
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H A D | registers.c | 28 {0x000, "TSEC_ID", "Controller ID register", ACC_RO, 0x01240000}, 29 {0x004, "TSEC_ID2", "Controller ID register 2", ACC_RO, 0x003000F0}, 30 {0x010, "IEVENT", "Interrupt event register", ACC_W1C, 0x00000000}, 31 {0x014, "IMASK", "Interrupt mask register", ACC_RW, 0x00000000}, 32 {0x018, "EDIS", "Error disabled register", ACC_RW, 0x00000000}, 33 {0x020, "ECNTRL", "Ethernet control register", ACC_RW, 0x00000040}, 34 {0x028, "PTV", "Pause time value register", ACC_RW, 0x00000000}, 35 {0x02C, "DMACTRL", "DMA control register", ACC_RW, 0x00000000}, 36 {0x030, "TBIPA", "TBI PHY address register", ACC_RW, 0x00000000}, 40 {0x058, "FIFO_RX_ALARM", "FIFO receive alarm start threshold register", ACC_RW, 0x00000… [all …]
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