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/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_vdec0_brdg_ctrl_masks.h24 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
25 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
28 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
29 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
32 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
33 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
36 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
37 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
40 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
41 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x
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/linux/drivers/media/i2c/s5c73m3/
H A Ds5c73m3.h44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x
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/linux/drivers/staging/fbtft/
H A Dfb_ili9320.c19 #define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \
20 "07 08 4 7 5 1 2 0 7 7"
24 u8 rxbuf[8] = {0, }; in read_devicecode()
26 write_reg(par, 0x0000); in read_devicecode()
38 if ((devcode != 0x0000) && (devcode != 0x9320)) in init_display()
40 "Unrecognized Device code: 0 in init_display()
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/linux/drivers/net/ethernet/hisilicon/hibmcge/
H A Dhbg_reg.h8 #define HBG_REG_SPEC_VALID_ADDR 0x0000
9 #define HBG_REG_EVENT_REQ_ADDR 0x0004
10 #define HBG_REG_MAC_ID_ADDR 0x0008
11 #define HBG_REG_PHY_ID_ADDR 0x000C
12 #define HBG_REG_MAC_ADDR_ADDR 0x0010
13 #define HBG_REG_MAC_ADDR_HIGH_ADDR 0x0014
14 #define HBG_REG_UC_MAC_NUM_ADDR 0x0018
15 #define HBG_REG_MDIO_FREQ_ADDR 0x0024
16 #define HBG_REG_MAX_MTU_ADDR 0x0028
17 #define HBG_REG_MIN_MTU_ADDR 0x002
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/linux/arch/powerpc/boot/dts/
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x0000000
[all...]
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_hw.h40 #define CSR_RING_ID 0x0008
44 #define CSR_RING_ID_BUF 0x000c
45 #define CSR_PBM_COAL 0x0014
46 #define CSR_PBM_CTICK0 0x0018
47 #define CSR_PBM_CTICK1 0x001c
48 #define CSR_PBM_CTICK2 0x0020
49 #define CSR_PBM_CTICK3 0x0024
50 #define CSR_THRESHOLD0_SET1 0x0030
51 #define CSR_THRESHOLD1_SET1 0x0034
52 #define CSR_RING_NE_INT_MODE 0x017
[all...]
/linux/arch/arm64/boot/dts/actions/
H A Ds900.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x
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/linux/arch/sparc/include/asm/
H A Dbbc.h17 #define BBC_AID 0x00 /* [B] Agent ID */
18 #define BBC_DEVP 0x01 /* [B] Device Present */
19 #define BBC_ARB 0x02 /* [B] Arbitration */
20 #define BBC_QUIESCE 0x03 /* [B] Quiesce */
21 #define BBC_WDACTION 0x04 /* [B] Watchdog Action */
22 #define BBC_SPG 0x06 /* [B] Soft POR Gen */
23 #define BBC_SXG 0x07 /* [B] Soft XIR Gen */
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
26 #define BBC_CSC 0x0
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/linux/drivers/media/radio/
H A Dsaa7706h.c28 $0FFF DSP CONTROL
29 $0A00 - $0FFE Reserved
37 #define SAA7706H_REG_CTRL 0x0fff
38 #define SAA7706H_CTRL_BYP_PLL 0x0001
39 #define SAA7706H_CTRL_PLL_DIV_MASK 0x003e
40 #define SAA7706H_CTRL_PLL3_62975MHZ 0x003e
41 #define SAA7706H_CTRL_DSP_TURBO 0x0040
42 #define SAA7706H_CTRL_PC_RESET_DSP1 0x0080
43 #define SAA7706H_CTRL_PC_RESET_DSP2 0x010
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/linux/include/sound/
H A Dwm8903.h15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x000
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/linux/drivers/gpu/drm/tests/
H A Ddrm_plane_helper_test.c20 DRM_MODE("1024x768", 0, 65000, 1024, 1048,
21 1184, 1344, 0, 768, 771, 777, 806, 0,
79 return 0; in drm_plane_helper_init()
88 KUNIT_ASSERT_GE_MSG(test, plane_state->src.x1, 0, in check_src_eq()
89 "src x coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
92 KUNIT_ASSERT_GE_MSG(test, plane_state->src.y1, 0, in check_src_eq()
93 "src y coordinate %x should never be below 0, src: " DRM_RECT_FP_FMT, in check_src_eq()
122 0, params->msg); in drm_test_check_plane_state()
140 .src = { 0,
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/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_1_7_msm8996.h13 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x454,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c
[all...]
H A Ddpu_3_0_msm8998.h12 .max_mixer_blendstages = 0x7,
25 .base = 0x0, .len = 0x458,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c
[all...]
/linux/drivers/clk/qcom/
H A Dvideocc-sm8250.c30 { 249600000, 2000000000, 0 },
34 .l = 0x25,
35 .alpha = 0x8000,
36 .config_ctl_val = 0x20485699,
37 .config_ctl_hi_val = 0x00002261,
38 .config_ctl_hi1_val = 0x329A699C,
39 .user_ctl_val = 0x00000000,
40 .user_ctl_hi_val = 0x00000805,
41 .user_ctl_hi1_val = 0x0000000
[all...]
/linux/arch/arc/boot/dts/
H A Dhsdk.dts22 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0>;
63 #clock-cells = <0>;
115 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
120 reg = <0x8a
[all...]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-bx50v3.dtsi48 #clock-cells = <0>;
103 #size-cells = <0>;
105 switch: switch@0 {
107 reg = <0>;
116 #size-cells = <0>;
121 #size-cells = <0>;
123 switchphy0: switchphy@0 {
124 reg = <0>;
126 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
160 pinctrl-0
[all...]
/linux/lib/zstd/decompress/
H A Dzstd_decompress_internal.h32 0, 1, 2, 3, 4, 5, 6, 7,
35 48, 64, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000,
36 0x2000, 0x4000, 0x800
[all...]
/linux/drivers/mtd/parsers/
H A Dbcm47xxpart.c28 #define BCM47XXPART_BYTES_TO_READ 0x4e8
31 #define BOARD_DATA_MAGIC 0x5246504D /* MPFR */
32 #define BOARD_DATA_MAGIC2 0xBD0D0BBD
33 #define CFE_MAGIC 0x43464531 /* 1EFC */
34 #define FACTORY_MAGIC 0x59544346 /* FCTY */
35 #define NVRAM_HEADER 0x48534C46 /* FLSH */
36 #define POT_MAGIC1 0x54544f50 /* POTT */
37 #define POT_MAGIC2 0x504f /* OP */
38 #define ML_MAGIC1 0x39685a42
39 #define ML_MAGIC2 0x2659413
[all...]
/linux/include/linux/
H A Dmhi_ep.h12 #define MHI_EP_DEFAULT_MTU 0x8000
247 * Return: 0 if driver registrations succeeds, a negative error code otherwise.
262 * Return: 0 if controller registrations succeeds, a negative error code otherwise.
277 * Return: 0 if power up succeeds, a negative error code otherwise.
301 * Return: 0 if the SKBs has been sent successfully, a negative error code otherwise.
/linux/drivers/media/usb/gspca/
H A Dsq905c.c34 #define SQ905C_MAX_TRANSFER 0x8000
36 #define FRAME_HEADER_LEN 0x50
39 #define SQ905C_CLEAR 0xa0 /* clear everything */
40 #define SQ905C_GET_ID 0x14f4 /* Read version number */
41 #define SQ905C_CAPTURE_LOW 0xa040 /* Starts capture at 160x120 */
42 #define SQ905C_CAPTURE_MED 0x1440 /* Starts capture at 320x240 */
43 #define SQ905C_CAPTURE_HI 0x2840 /* Starts capture at 320x240 */
46 #define SQ905C_CAPTURE_INDEX 0x110f
60 * The 0x277
[all...]
/linux/drivers/fwctl/mlx5/
H A Dmain.c31 u8 opcode[0x10];
32 u8 uid[0x10];
34 u8 reserved_at_20[0x10];
35 u8 op_mod[0x10];
37 u8 reserved_at_40[0x40];
41 u8 status[0x8];
42 u8 reserved_at_8[0x18];
44 u8 syndrome[0x20];
46 u8 reserved_at_40[0x40];
50 MLX5_UCTX_OBJECT_CAP_TOOLS_RESOURCES = 0x
[all...]
/linux/drivers/comedi/drivers/
H A Dicp_multi.c24 * 12-bit resolution. Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.
41 #define ICP_MULTI_ADC_CSR 0x00 /* R/W: ADC command/status register */
42 #define ICP_MULTI_ADC_CSR_ST BIT(0) /* Start ADC */
43 #define ICP_MULTI_ADC_CSR_BSY BIT(0) /* ADC busy */
45 #define ICP_MULTI_ADC_CSR_RA BIT(5) /* Input range 0 = 5V, 1 = 10V */
47 #define ICP_MULTI_ADC_CSR_DI_CHAN(x) (((x) & 0x7) << 9)
48 #define ICP_MULTI_ADC_CSR_SE_CHAN(x) (((x) & 0xf) << 8)
50 #define ICP_MULTI_DAC_CSR 0x04 /* R/W: DAC command/status register */
51 #define ICP_MULTI_DAC_CSR_ST BIT(0) /* Start DAC */
52 #define ICP_MULTI_DAC_CSR_BSY BIT(0) /* DA
[all...]
/linux/drivers/s390/crypto/
H A Dzcrypt_ccamisc.h18 #define TOKTYPE_NON_CCA 0x00 /* Non-CCA key token */
19 #define TOKTYPE_CCA_INTERNAL 0x01 /* CCA internal sym key token */
20 #define TOKTYPE_CCA_INTERNAL_PKA 0x1f /* CCA internal asym key token */
23 #define TOKVER_PROTECTED_KEY 0x01 /* Protected key token */
24 #define TOKVER_CLEAR_KEY 0x02 /* Clear key token */
27 #define TOKVER_CCA_AES 0x04 /* CCA AES key token */
28 #define TOKVER_CCA_VLSC 0x05 /* var length sym cipher key token */
42 /* inside view of a CCA secure key token (only type 0x01 version 0x04) */
44 u8 type; /* 0x0
[all...]
/linux/arch/s390/include/asm/
H A Dqdio.h23 #define QDIO_QETH_QFMT 0
28 * struct qdesfmt0 - queue descriptor, format 0
49 #define QDR_AC_MULTI_BUFFER_ENABLE 0x01
85 #define QIB_AC_OUTBOUND_PCI_SUPPORTED 0x40
86 #define QIB_RFLAGS_ENABLE_QEBSM 0x80
87 #define QIB_RFLAGS_ENABLE_DATA_DIV 0x02
174 #define SBAL_EFLAGS_LAST_ENTRY 0x40
175 #define SBAL_EFLAGS_CONTIGUOUS 0x20
176 #define SBAL_EFLAGS_FIRST_FRAG 0x04
177 #define SBAL_EFLAGS_MIDDLE_FRAG 0x0
[all...]
/linux/drivers/media/rc/
H A Dir-rc6-decoder.c12 * RC6-0-16 (standard toggle bit in header)
30 #define RC6_MODE_MASK 0x07 /* for the header bits */
31 #define RC6_STARTBIT_MASK 0x08 /* for the header bits */
32 #define RC6_6A_MCE_TOGGLE_MASK 0x8000 /* for the body bits */
33 #define RC6_6A_LCC_MASK 0xffff0000 /* RC6-6A-32 long customer code mask */
34 #define RC6_6A_MCE_CC 0x800f0000 /* MCE customer code */
35 #define RC6_6A_ZOTAC_CC 0x80340000 /* Zotac customer code */
36 #define RC6_6A_KATHREIN_CC 0x80460000 /* Kathrein RCU-676 customer code */
62 case 0 in rc6_mode()
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